IR3522 International Rectifier, IR3522 Datasheet - Page 19

• Manufacturer Part Number: IR3522
• Description: DDR & VTT CONTROL IC
• Manufacturer: International Rectifier

IR3522
Remote Voltage Sensing
VOSEN
+ and VOSEN
- are used for remote sensing and are connected directly to the load. The remote sense
X
X
differential amplifiers are high speed, have low input offset and low input bias currents to ensure accurate voltage
sensing and fast transient response.
Start-up Sequence
The IR3522 is designed as a chipset with the IR3506 Phase IC to achieve output voltage tracking. VOUT2’s
internal reference (VREF_TRACK) is generated by a divided-by-half internal resistor divider. This will ensure
VOUT2 remains half the value of VOUT1 preventing possible damage to some DDR system’s microprocessors. In
addition, a track-fault comparator is implemented to monitor both outputs which will further guarantee the outputs
remain at least 1.0 V apart and will generate a fault if this limit is surpassed, further protecting the DDR system.
When VCCL is applied to the IC and the SS/DEL is below 0.3V, IIN1 (only) is pulled up to VCCL through an internal
PFET enabling a diode emulation preset latch on the IR3506 phase IC. Diode emulation mode ensures proper
current sharing during system soft-start by turning off the bottom sync FET when negative inductor current is
sensed via the CSIN- and CSIN+ pins. The IIN1 pin is release once SS/DEL charges above 0.3 V. Once VOUT1
reaches 75% of its final operating value, the diode emulation mode is reset allowing the phase ICs to sink current.
The IR3522 has a programmable soft-start and soft-stop function. The soft-start helps limit the surge current during
the converter start-up, whereas the soft-stop is needed to maintain output tracking during system turn-off. A
capacitor connected between the SS/DEL and LGND pins controls timing. A constant source and sink current
control the charge and discharge rates of the SS/DEL.
Figure 10 depicts the SVID start-up sequence. When the ENABLE input is asserted and there are no faults, the
SS/DEL pin will begin charging. If the IC receives a SVID communication prior to the ENABLE pin going high, the
output ramps up to the program value listed in Table 2, otherwise the VOUT1 and VOUT2 default to 1.5 V and 0.75
V, respectively. The error amplifier output, EAOUT
is clamped low until SS/DEL reaches 1.4V. The error amplifier
x,
will then regulate the converter’s output voltage to match the V(SS/DEL)-1.4V offset until the converter output
reaches the SVID code or default state. The SS/DEL voltage continues to increase until it rises above the threshold
of Delay Comparator where the PGOOD output is allowed to go high.
A low signal on the ENABLE or VID_OFF input immediately sets the fault latch, which causes the EAOUT pin to
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drive low, thereby turning off the phase IC drivers. The PGOOD pin also drives low and SS/DEL discharges to 0.2V.
If the fault has cleared, the fault latch will be reset by the SS/DEL discharge comparator allowing another soft start
charge cycle to occur.
All other faults (See Table 5) will set a different fault latch that can only be reset by cycling ENABLE or the
VID_OFF SVID command. These faults discharge SS/DEL, pull down EAOUT
, pull up CROWBAR to VCCLDRV
X
and drive PGOOD low. The CROWBAR circuit is design to drive an external NMOS device to pull the output
voltage to ground. This feature minimizes negative voltage undershoots at the output by reducing sync FET current
during fault events.
The converter can be disabled by pulling the SS/DEL pins below 0.6V
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