LTC1266 Linear Technology, LTC1266 Datasheet - Page 14

• Manufacturer Part Number: LTC1266
• Description: Synchronous Regulator Controller for N- or P-Channel MOSFETs
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC1266
LTC1266-3.3/LTC1266-5
discharge C
current change and returns V
During this recovery time V
overshoot or ringing which would indicate a stability
problem. The Pin 7 external components shown in the
Figure 1 circuit will prove adequate compensation for
most applications.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
where L1, L2, etc., are the individual losses as a percent-
age of input power. (For high efficiency circuits, only small
errors are incurred by expressing losses as a percentage
of output power).
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of the
losses in LTC1266 series circuits: 1) LTC1266 DC bias
current, 2) MOSFET gate charge current and 3) I
1. The DC supply current is the current which flows into
2. MOSFET gate charge current results from switching the
14
% Efficiency = 100% – (L1 + L2 + L3 + ...)
V
current is 170 A for no load, and increases proportion-
ally with load up to a constant 2.1mA after the LTC1266
series has entered continuous mode. Because the DC
bias current is drawn from V
increases with input voltage. For V
losses are generally less than 1% for load currents over
30mA. However, at very low load currents the DC bias
current accounts for nearly all of the loss.
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from Power V
The resulting dQ/dt is a current flowing into Power V
(Pin 5) which is typically much larger than the DC
supply current. In continuous mode, I
Q
IN
P
). The typical gate charge for a 0.05
(Pin 2). For V
OUT
until the regulator loop adapts to the
U U
IN
= 10V the LTC1266 DC supply
OUT
OUT
to its steady-state value.
can be monitored for
IN
W
, the resulting loss
IN
GATECHG
= 5V the DC bias
IN
to ground.
N-channel
2
R losses.
U
= f (Q
N
IN
+
3. I
Figure 8 shows how the efficiency losses in a typical
LTC1266 series regulator end up being apportioned. The
gate charge loss is responsible for the majority of the
efficiency lost in the mid-current region. If Burst Mode
operation was not employed at low currents, the gate
charge loss alone would cause efficiency to drop to
power MOSFET is 15nC. This results in I
in 200kHz continuous operation for a 2% to 3% typical
mid-current loss with V
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it ar-
gues against using larger MOSFETs than necessary to
control I
well as money!
of the MOSFET, inductor and current shunt. In continu-
ous mode the average output current flows through L
and R
bottom-side MOSFETs. If the two MOSFETs have ap-
proximately the same R
one MOSFET can simply be summed with the resis-
tances of L and R
example, if each R
R
results in losses ranging from 3.5% to 15% as the
output current increases from 1A to 5A. I
cause the efficiency to roll off at high output currents.
2
SENSE
R losses are easily predicted from the DC resistances
SENSE
= 0.02 , then the total resistance is 0.12 . This
100
95
90
85
80
2
0.01
R losses, since overkill can cost efficiency as
, but is “chopped” between the topside and
LTC1266 I
Figure 8. Efficiency Loss
0.03
GATE CHARGE
Q
DS(ON)
SENSE
0.1
I
OUT
IN
DS(ON)
= 5V.
(A)
= 0.05 , R
to obtain I
0.3
, then the resistance of
1
LTC1266 • F08
I
2
R
2
L
GATECHG
R losses. For
5
= 0.05
2
R losses
= 6mA
and