LTC1266 Linear Technology, LTC1266 Datasheet - Page 15

• Manufacturer Part Number: LTC1266
• Description: Synchronous Regulator Controller for N- or P-Channel MOSFETs
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
unacceptable levels (see Figure 7). With Burst Mode
operation, the DC supply current represents the lone (and
unavoidable) loss component which continues to become
a higher percentage as output current is reduced. As
expected the I
Other losses including C
losses, MOSFET switching losses, Schottky conduction
losses during deadtime and inductor core losses, gener-
ally account for less than 2% total additional loss.
Design Example
As a design example, assume V
V
can immediately be calculated:
Assume that the MOSFET dissipations are to be limited to
P
If T
is 50 C/ W, then the junction temperatures will be 140 C
and
can now be calculated:
The topside FET requirement can be met by an N-channel
Si9410DY which has an R
V
by an Si9410DY. Note that the most stringent requirement
for the bottom-side MOSFET is with V
circuit). During a continuous short circuit, the worst-case
dissipation rises to:
With the 0.02 sense resistor, I
increasing the 0.04 bottom-side FET dissipation to 2.3W.
OUT
T
GS
R
t
C
L
P
TS R
BS R
= P
OFF
A
MIN
T
B
SENSE
= 5V. The bottom-side FET requirement is exceeded
= 40 C and the thermal resistance of each MOSFET
T
= 3.3V, I
= 1.7 s/(1.3 10
= I
B
=
= (1/200kHz) [1 – (3.3/5)] = 1.7 s
= 5.1 10
DS(ON)
= 2W.
DS(ON)
SC(AVG)
B
= 100mV/5 = 0.02
= 0.60. The required R
MAX
2
R losses dominate at high load currents.
=
=
2
= 5A and f = 200kHz; R
5
3.3(5)
1.7(5)
R
U U
DS(ON)
0.02
4
) = 130pF
5(2)
5(2)
2
2
IN
(1.60)
(1.60)
DS(ON)
and C
(1 +
130pF 3.3V = 5 H
SC(AVG)
DS(ON)
= 0.076
= 0.147
OUT
IN
B
W
of about 0.04
)
OUT
= 5V (nominal),
for each MOSFET
ESR dissipative
SENSE
= 0 (i.e., short
6A will result,
, C
U
T
and L
at
C
temperature and C
optimum efficiency.
Now allow V
V
voltage drop across the topside FET,
At this lower input voltage, the operating frequency de-
creases and the topside FET will be conducting most of the
time, causing the power dissipation to increase.
At dropout,
This last step is necessary to assure that the power
dissipation and junction temperature of the topside FET
are not exceeded.
These last calculations assume that Power V
enough to keep the topside FET fully turned on at dropout,
as would be the case with the Figure 11circuit. If this isn’t
true (as with the Figure 1 circuit) the R
which in turn increases V
Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1266 adjustable version is used with an external
resistive divider from V
voltage is determined by:
To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1266.
For Figure 1 applications with V
R
inputs operate near ground. When the current comparator
is operated at less than 2V common mode, the off-time
increases approximately 40%, requiring the use of a
smaller timing capacitor C
V
IN
IN
SENSE
MIN
P
f
V
MIN
will require an RMS current rating of at least 2.5A at
can be calculated from the maximum duty cycle and
T
OUT
= I
=
is moved to ground, the current sense comparator
=
V
2
= 1.25 1 + R2
LOAD
OUT
t
ON (MAX)
IN
+ I
to drop to its minimum value. The minimum
LTC1266-3.3/LTC1266-5
LOAD
R
1
DS(ON)
OUT
+ t
R1
OFF
will require an ESR of 0.02 for
OUT
(R
D
MIN
= 16kHz
MAX
T
DS(ON)
(1 +
.
to V
and P
FB
OUT
T
+ R
, Pin 10. The regulated
) D
T
.
L
below 2V, or when
DS(ON)
+ R
MAX
LTC1266
SENSE
will increase
IN
)
= 4.0V
15
is high