LTC1415 Linear Technology, LTC1415 Datasheet - Page 18

• Manufacturer Part Number: LTC1415
• Description: 12-Bit/ 1.25Msps/ 55mW Sampling A/D Converter
• Manufacturer: Linear Technology

APPLICATIONS
LTC1415
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a
conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.70 s and a maximum conversion time over the
full operating temperature range of 0.75 s. No external
adjustments are required. The guaranteed maximum
acquisition time is 150ns. In addition, a throughput time of
800ns and a minimum sampling rate of 1.25Msps are
guaranteed.
Power Shutdown
The LTC1415 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The
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INFORMATION
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Figure 13d. Suggested Evaluation Circuit Board Solder Side Layout
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Nap mode reduces the power by 87% and leaves only the
digital logic and reference powered up. The wake-up time
from Nap to active is 200ns. Follow the setup time shown
in Figure 14a to avoid inadvertently invoking Sleep mode.
In Sleep mode all bias currents are shut down and only
leakage current remains, about 1 A. Wake-up time from
Sleep mode is much slower since the reference circuit
must power up and settle to 0.01% for full 12-bit accu-
racy. Sleep mode wake-up time is dependent on the value
of the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 10ms with the recommended 10 F
capacitor. Shutdown is controlled by Pin 21 (SHDN); the
ADC is in shutdown when it is low. The shutdown mode is
selected with Pin 20 (NAP/SLP); high selects Nap.
NAP/SLP
SHDN
Figure 14a. NAP/SLP to SHDN Timing
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1415 F14a