LTC2262-12 Linear Dimensions Semiconductor, LTC2262-12 Datasheet - Page 18

• Manufacturer Part Number: LTC2262-12
• Description: 150Msps Ultralow Power 1.8V ADC
• Manufacturer: Linear Dimensions Semiconductor

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LTC2262-12
APPLICATIONS INFORMATION
Overfl ow Bit
The overfl ow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overfl ow bit has the same pipeline latency as the
data bits.
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT
so the rising edge of CLKOUT
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT
setup-and-hold time when latching the data, the CLKOUT
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2262-12 can also phase shift the CLKOUT
CLKOUT
trol register A2. The output clock can be shifted by
0°, 45°, 90° or 135°. To use the phase shifting feature
the clock duty cycle stabilizer must be turned on.
18
–
signals by serially programming mode con-
D0-D11, OF
CLKOUT
ENC
+
+
+
can be used to latch the
+
. To allow adequate
Figure 14. Phase Shifting CLKOUT
+
+
+
,
/
Another control register bit can invert the polarity of
CLKOUT
The combination of these two features enables phase
shifts of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overfl ow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
A
(2V RANGE)
>+1.000000V
+0.999512V
+0.999024V
+0.000488V
–0.000488V
–0.000976V
–0.999512V
–1.000000V
≤–1.000000V
226212 F14
0.000000V
IN
PHASE
+
SHIFT
135°
180°
225°
270°
315°
45°
90°
0°
– A
IN
–
+
CLKINV
and CLKOUT
0
0
0
0
1
1
1
1
OF
MODE CONTROL BITS
1
0
0
0
0
0
0
0
0
1
CLKPHASE1
(OFFSET BINARY)
1111 1111 1111
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
D11-D0
0
0
1
1
0
0
1
1
–
, independently of the phase shift.
CLKPHASE0
0
1
0
1
0
1
0
1
(2’s COMPLEMENT)
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
D11-D0
226212p