LTC2262-14 Linear Dimensions Semiconductor, LTC2262-14 Datasheet
LTC2262-14
Related parts for LTC2262-14
LTC2262-14 Summary of contents
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... CLOCK Ultralow Power 1.8V ADC DESCRIPTION The LTC signed for digitizing high frequency, wide dynamic range signals. The LTC2262-14 is perfect for demanding commu- nications applications with AC performance that includes 72.8dB SNR and 88dB spurious free dynamic range (SFDR Ultralow jitter of 0.17ps ...
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... LTC2262-14 ABSOLUTE MAXIMUM RATINGS Supply Voltages ( ....................... –0. Analog Input Voltage ( PAR/SER, SENSE) (Note 3) ...........–0. www.datasheet4u.com + Digital Input Voltage (ENC , ENC SDI, SCK) (Note 4) .................................... –0.3V to 3.9V SDO (Note 4) ............................................ –0.3V to 3.9V PIN CONFIGURATIONS FULL-RATE CMOS OUTPUT MODE TOP VIEW ...
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... Differential Analog Input (Note Per Pin, 150Msps + – 0 < < Encode < PAR/SER < 0.625 < SENSE < 1.3V Figure 6 Test Circuit LTC2262-14 TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C MIN TYP MAX –3.75 ±1 3.75 l –0.9 ±0.3 0.9 l – ...
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... LTC2262-14 DYNAMIC ACCURACY otherwise specifi cations are 25° SYMBOL PARAMETER SNR Signal-to-Noise Ratio www.datasheet4u.com SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic Spurious Free Dynamic Range 4th Harmonic or Higher S/(N+D) Signal-to-Noise Plus Distortion Ratio INTERNAL REFERENCE CHARACTERISTICS full operating temperature range, otherwise specifi ...
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... A CONDITIONS (Note 10) (Note 10) DC Input Sine Wave Input Sine Wave Input, OV =1. Input Sine Wave Input, OV =1.2V DD LTC2262-14 MIN TYP MAX l 1.3 l 0.6 l – 200 l –10 ...
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... LTC2262-14 POWER REQUIREMENTS range, otherwise specifi cations are at T SYMBOL PARAMETER LVDS Output Mode www.datasheet4u.com V Analog Supply Voltage DD OV Output Supply Voltage DD I Analog Supply Current VDD I Digital Supply Current OVDD (0V = 1.8V Power Dissipation DISS All Output Modes P Sleep Mode Power ...
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... Note 10: Recommended operating conditions. Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels – – – LTC2262-14 MIN TYP MAX 250 125 = ...
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... LTC2262-14 TIMING DIAGRAMS www.datasheet4u.com ANALOG INPUT – ENC + ENC D0_1 • • • D12_13 OF + CLKOUT – CLKOUT ANALOG INPUT – ENC + ENC + D0_1 – D0_1 • • • + D12_13 – D12_13 + OF – CLKOUT – CLKOUT 8 Double Data Rate CMOS Output Mode Timing ...
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... OUTPUT CODE 226214 G01 LTC2262-14 t SCK LTC2262-14: 8k Point FFT, f –1dBFS, 150Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 12288 16384 FREQUENCY (MHz) 226214 G02 ...
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... INPUT LEVEL (dBFS) 226214 G10 = 70MHz LTC2262-14: 8k Point FFT –1dBFS, 150Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 60 70 ...
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... When SCK is low, the full-rate CMOS output mode is enabled. When SCK is high, the double data rate LVDS output mode (with 3.5mA output current) is enabled. SCK can be driven with 1.8V to 3.3V logic. LTC2262-14 LTC2262-14: SNR vs Sample Rate and Digital Output Mode, 30MHz Sine Wave Input, –1dB 73 72 ...
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... LTC2262-14 PIN FUNCTIONS SDI (Pin 15): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge www.datasheet4u.com of SCK. In the parallel programming mode (PAR/SER = V ), SDI can be used to power down the part. When SDI DD is low, the part operates normally ...
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... INTERNAL CLOCK SIGNALS DIFF CLOCK/DUTY REF CYCLE AMP CONTROL REFH REFL 0.1μF + – PAR/SER ENC ENC 2.2μF 0.1μF 0.1μF Figure 1. Functional Block Diagram LTC2262- The phase FIFTH PIPELINED ADC STAGE GND SHIFT REGISTER AND CORRECTION D13 • MODE • OUTPUT CONTROL • ...
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... LTC2262-14 APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2262- low power 14-bit 150Msps A/D www.datasheet4u.com converter that is powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially, or single ended for lower power consumption. The digital outputs can be CMOS, ...
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... Input Frequencies Above 270MHz LTC2262-14 50Ω 0.1μ 0.1μF 25Ω 1.8pF 25Ω – 50Ω 0.1μF 0.1μF 2.7nH + A IN LTC2262-14 0.1μF 25Ω T1 0.1μF 25Ω 2.7nH – T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE LTC2262-14 226214 F05 226214 F06 226214p 15 ...
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... LTC2262-14 APPLICATIONS INFORMATION Reference The LTC2262-14 has an internal 1.25V voltage reference. www.datasheet4u.com For a 2V input range using the internal reference, connect SENSE For a 1V input range using the external DD reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9 ...
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... V (up to 3.6V should have fast 0.1μF + ENC T1 1:4 100Ω 100Ω – ENC 0.1μF Figure 12. Sinusoidal Encode Drive 0.1μF + ENC PECL OR LTC2262-14 LVDS CLOCK 0.1μF – ENC 226214 F13 Figure 13. PECL or LVDS Encode Drive + threshold LTC2262-14 226214 F12 226214p 17 ...
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... DIGITAL OUTPUTS Digital Output Modes The LTC2262-14 can operate in three digital output modes: full rate CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system). The output mode is set by mode control register A3 (serial programming mode SCK (parallel programming mode) ...
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... CLKOUT signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. The LTC2262-14 can also phase shift the CLKOUT – CLKOUT signals by serially programming mode con- trol register A2. The output clock can be shifted by 0° ...
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... Recovering from nap CLKOUT OF D13/D0 D12/D0 • • • D2/D0 D1/D0 D0 226214 F15 PC BOARD FPGA CLKOUT OF D13/D0 D13 D12/D0 LTC2262-14 D12 • • D2/D0 • D2 D1/ 226214 F16 Figure 16. Unrandomizing a Randomized Digital Output Signal , REF 226214p ...
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... Nap mode is enabled by mode control register A1 in the serial programming mode. DEVICE PROGRAMMING MODES The operating modes of the LTC2262-14 can be pro- grammed by either a parallel interface or a simple serial interface. The serial interface has more fl exibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes ...
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... Ground fi ll and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the LTC2262-14 is transferred REF from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board ...
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... Two’s Complement Data Format Note: ABP = 1 Forces the Output Format to be Offset Binary ILVDS1 ILVDS0 TERMON Digital Output Mode Control Bits OUTTEST2 OUTTEST1 OUTTEST0 Digital Output Test Pattern Bits LTC2262- OUTOFF OUTMODE1 OUTMODE0 ABP RAND TWOSCOMP 23 226214p ...
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... LTC2262-14 TYPICAL APPLICATIONS www.datasheet4u.com T2 MABAES0060 R9 10Ω • • ANALOG INPUT R10 10Ω R15 100Ω C12 C13 0.1μF 1μF 24 LTC2262 Evaluation Board Schematic SENSE R39 33.2Ω 1% R14 C51 1k 4.7pF R40 33.2Ω 1% C17 1μF C19 0.1μ SENSE V DD R27 10Ω ...
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... TYPICAL APPLICATIONS Silkscreen Top www.datasheet4u.com Inner Layer 2 GND 226214 TA03 226214 TA04 LTC2262-14 Top Side 226214 TA04 Inner Layer 3 226214 TA06 226214p 25 ...
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... LTC2262-14 TYPICAL APPLICATIONS Inner Layer 4 www.datasheet4u.com 26 226214 TA07 Bottom Side 226214 TA09 Inner Layer 5 Power 226214 TA08 226214p ...
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... LTC DWG # 05-08-1728 Rev Ø) 0.70 ±0.05 6.50 ±0.05 5.10 ±0.05 4.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 0.75 ± 0. 0.10 TYP 4.50 REF (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2262- 0.115 TYP 39 40 0.40 ± 0. PIN 1 NOTCH R = 0.45 OR 0.35 45° CHAMFER 4.42 ±0.10 4.42 ±0.10 (UJ40) QFN REV Ø 0406 0.25 ± 0.05 0.50 BSC BOTTOM VIEW— ...
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... LTC2262-14 RELATED PARTS PART NUMBER DESCRIPTION LTC1993-2 High Speed Differential Op Amp www.datasheet4u.com LTC1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifi er/Driver LTC2215 16-Bit, 65Msps, Low Noise ADC LTC2216 16-Bit, 80Msps, Low Noise ADC LTC2217 16-Bit, 105Msps, Low Noise ADC LTC2202 16-Bit, 10Msps, 3 ...