LTC2283 Linear Technology, LTC2283 Datasheet - Page 8

• Manufacturer Part Number: LTC2283
• Description: 125Msps Low Power 3V ADC
• Manufacturer: Linear Technology

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PIN FUNCTIONS
LTC2283
A
Input.
A
Input.
REFHA (Pins 3, 4): Channel A High Reference. Short to-
gether and bypass to Pins 5, 6 with a 0.1μF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2μF ceramic chip capacitor
and to ground with a 1μF ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short to-
gether and bypass to Pins 3, 4 with a 0.1μF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2μF ceramic chip capacitor
and to ground with a 1μF ceramic chip capacitor.
V
GND with 0.1μF ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1μF ceramic
chip capacitor as close to the pin as possible. Also by-
pass to Pins 13, 14 with an additional 2.2μF ceramic
chip capacitor and to ground with a 1μF ceramic chip
capacitor.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1μF ceramic
chip capacitor as close to the pin as possible. Also by-
pass to Pins 11, 12 with an additional 2.2μF ceramic
chip capacitor and to ground with a 1μF ceramic chip
capacitor.
A
Input.
A
Input.
GND (Pins 17, 64): ADC Power Ground.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to V
8
INA
INA
DD
INB
INB
+
–
–
+
(Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
(Pin 2): Channel A Negative Differential Analog
(Pin 15): Channel B Negative Differential Analog
(Pin 16): Channel B Positive Differential Analog
(Pin 1): Channel A Positive Differential Analog
CMB
selects the internal reference
and a ±0.5V input range. V
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of ±V
V
Mode Bias. Bypass to ground with 2.2μF ceramic chip
capacitor. Do not connect to V
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA11; Channel B
comes out on DB0-DB11. If MUX is Low, the output bus-
ses are swapped and Channel A comes out on DB0-DB11;
Channel B comes out on DA0-DA11. To multiplex both
channels onto a single output bus, connect MUX, CLKA
and CLKB together. (This is not recommended at clock
frequencies above 80Msps.)
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to V
with the outputs at high impedance. Connecting SHDNB
to V
outputs at high impedance. Connecting SHDNB to V
and OEB to V
at high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24, 25, 41, 42): Do not connect these pins.
DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital
Outputs. DB11 is the MSB.
OGND (Pins 31, 50): Output Driver Ground.
OV
Bypass to ground with 0.1μF ceramic chip capacitor.
CLKOUT (Pin 40): Data Ready Clock Output. Latch data
on the falling edge of CLKOUT. CLKOUT is derived from
CLKB. Tie CLKA to CLKB for simultaneous operation.
DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital
Outputs. DA11 is the MSB.
OF (Pin 57): Overfl ow/Underfl ow Output. High when an
overfl ow or underfl ow has occurred on either Channel A
or Channel B.
CMB
DD
DD
(Pin 20): Channel B 1.5V Output and Input Common
(Pins 32, 49): Positive Supply for the Output Drivers.
and OEB to GND results in nap mode with the
SENSEB
DD
results in sleep mode with the outputs
. ±1V is the largest valid input range.
DD
DD
selects the internal reference
CMA
results in normal operation
.
2283fb
DD