LTC2309 Linear Technology Corporation, LTC2309 Datasheet - Page 13

• Manufacturer Part Number: LTC2309
• Description: 12-Bit SAR ADC
• Manufacturer: Linear Technology Corporation

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Each device on the I
address stored in the device and can only operate either
as a transmitter or receiver, depending on the function
of the device. A device can also be considered as a
master or a slave when performing data transfers. A
master is the device which initiates a data transfer on
the bus and generates the clock signals to permit the
transfer. Devices addressed by the master are consid-
ered slaves.
The LTC2309 can only be addressed as a slave (see
Table 2). Once addressed, it can receive confi guration
bits (D
serial clock line (SCL) is always an input to the LTC2309
and the serial data line (SDA) is bidirectional. The device
supports the standard mode and the fast mode for data
transfer speeds up to 400kbits/s (see Timing Diagram
section for defi nition of the I
The Start and Stop Conditions
Referring to Figure 7, a Start (S) condition is generated
by transitioning SDA from high to low while SCL is
high. The bus is considered to be busy after the Start
condition. When the data transfer is fi nished, a Stop
(P) condition is generated by transitioning SDA from
low to high while SCL is high. The bus is free after a
Stop condition is generated. Start and Stop conditions
are always generated by the master.
When the bus is in use, it stays busy if a Repeated
Start (Sr) is generated instead of a Stop condition.
The Repeated Start timing is functionally identical to
the Start and is used for writing and reading from the
device before the initiation of a new conversion.
APPLICATIONS INFORMATION
SDA
SCL
Figure 7. Timing Diagrams of Start and Stop Conditions
IN
Start Condition
word) or transmit the last conversion result. The
S
2
C bus is recognized by a unique
SDA
SCL
2
C timing).
Stop Condition
P
2309 F07
Data Transferring
After the Start condition, the I
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of
nine bits, one byte followed by one acknowledge (ACK)
bit. The master releases the SDA line during the ninth
SCL clock cycle. The slave device can issue an ACK by
pulling SDA low or issue a Not Acknowledge (NAK)
by leaving the SDA line high impedance (the external
pull-up resistor will hold the line high). Change of data
only occurs while the SCL line is low.
Data Format
After a Start condition, the master sends a 7-bit ad-
dress followed by a read/write (R/W) bit. The R/W
bit is 1 for a read request and 0 for a write request.
If the 7-bit address matches one of the LTC2309’s
9 pin-selectable addresses, the ADC is selected. When
the ADC is addressed during a conversion, it will not
acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2309 issues an ACK by pulling the SDA line low.
The LTC2309 has two registers. The 12-bit wide output
register contains the last conversion result. The 6-bit
wide input register confi gures the input MUX and the
operating mode of the ADC.
Output Data Format
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters either nap or sleep mode depending on the
setting of the SLP bit (see Nap Mode and Sleep Mode
sections). When the LTC2309 is addressed for a read
operation, it acknowledges by pulling SDA low and acts
as a transmitter. The master/receiver can read up to two
bytes from the LTC2309. After a complete read opera-
tion of 2 bytes, a Stop condition is needed to initiate a
new conversion. The device will NAK subsequent read
operations while a conversion is being performed.
2
C bus is busy and data
LTC2309
13
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