LTC2351-14 Linear Technology, LTC2351-14 Datasheet - Page 16

• Manufacturer Part Number: LTC2351-14
• Description: 1.5Msps Simultaneous Sampling ADC
• Manufacturer: Linear Technology

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LTC2351-14
APPLICATIO S I FOR ATIO
POWER-DOWN MODES
Upon power-up, the LTC2351-14 is initialized to the
active state and is ready for conversion. The Nap and Sleep
mode waveforms show the power down modes for the
LTC2351-14. The SCK and CONV inputs control the power
down modes (see Timing Diagrams). Two rising edges at
CONV, without any intervening rising edges at SCK, put
the LTC2351-14 in Nap mode and the power consumption
drops from 16.5mW to 4.5mW. The internal reference
remains powered in Nap mode. One or more rising edges
at SCK wake up the LTC2351-14 very quickly and CONV
can start an accurate conversion within a clock cycle. Four
rising edges at CONV, without any intervening rising
edges at SCK, put the LTC2351-14 in Sleep mode and the
power consumption drops from 16.5mW to 12µW. One or
more rising edges at SCK wake up the LTC2351-14 for
operation. The internal reference (V
and settle with a 10µF load. Using sleep mode more
frequently compromises the accuracy of the output data.
Note that for slower conversion rates, the Nap and Sleep
modes can be used for substantial reductions in power
consumption.
DIGITAL INTERFACE
The LTC2351-14 has a 3-wire SPI (Serial Peripheral Inter-
face) interface. The SCK and CONV inputs and SDO output
implement this interface. The SCK and CONV inputs
accept swings from 3V logic and are TTL compatible, if the
logic swing does not exceed V
the three serial port signals follows:
16
U
U
DD
. A detailed description of
REF
W
) takes 2ms to slew
U
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quent rising edges at CONV are ignored by the LTC2351-14
until the following 96 SCK rising edges have occurred. The
duty cycle of CONV can be arbitrarily chosen to be used as
a frame sync signal for the processor serial port. A simple
approach to generate CONV is to create a pulse that is one
SCK wide to drive the LTC2351-14 and then buffer this
signal to drive the frame sync input of the processor
serial port. It is good practice to drive the LTC2351-14
CONV input first to avoid digital noise interference during
the sample-to-hold transition triggered by CONV at the
start of conversion. It is also good practice to keep the
width of the low portion of the CONV signal greater than
15ns to avoid introducing glitches in the front end of the
ADC just before the sample-and-hold goes into Hold mode
at the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sine
waves above 100kHz are sampled, the CONV signal must
have as little jitter as possible (10ps or less). The square
wave output of a common crystal clock module usually
meets this requirement. The challenge is to generate a
CONV signal from this crystal clock without jitter corrup-
tion from other digital circuits in the system. A clock
divider and any gates in the signal path from the crystal
clock to the CONV input should not share the same
integrated circuit with other parts of the system. The SCK
and CONV inputs should be driven first, with digital buffers
235114f