LTC2362 Linear Technology, LTC2362 Datasheet - Page 15

• Manufacturer Part Number: LTC2362
• Description: (LTC2360 - LTC2362) 12-Bit Serial ADCs
• Manufacturer: Linear Technology

ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 0.5mA, 0.75mA and
1.1mA for the LTC2360/LTC2361/LTC2362 and automati-
cally entering sleep mode right after a conversion, these
devices achieve extremely low power consumption over
a wide range of sample rates (see Figure 11). The sleep
mode allows the supply current to drop with reduced
sample rate. Several things must be taken into account
to achieve such low power consumption.
Minimize Power Consumption in Sleep Mode
The LTC2360/LTC2361/LTC2362 enter sleep mode after
each conversion if CONV remains high and draw only
leakage current (see Figure 10). If the CONV input is not
running rail-to-rail, the input logic buffer will draw current.
This current may be large compared to the typical supply
APPLICATIONS INFORMATION
Figure 12. Minimize the Time When the Device Draws Power, While the Conversion Results are Available After the Device Wakes Up
CONV
SDO
SCK
1200
1000
Figure 11. Supply Current vs Sample Rate
800
600
400
200
0
1
V
T
A
DD
= 25°C
= OV
1
B11
DD
SAMPLING INPUT AND
TRANSFERRING DATA
SAMPLE RATE (ksps)
= V
2
10
B10
LTC2360
REF
= 3.6V
3
B9
LTC2361
4
100
t
ACQ
9
B3
LTC2362
10
236012 TA01b
B2
1000
11
B1
12
B0
t
THROUGHPUT
EXECUTING A CONVERSION AND PUTTING
THE DEVICE INTO SLEEP MODE
t
CONV
= t
ACQ
current. To obtain the lowest supply current, bring the CONV
pin to GND when it is low and to V
After the conversion with CONV staying high, the converter
is in sleep mode and draws only leakage current. The status
of the SCK input has no effect on supply current during
this time. For the best performance, hold SCK either high
or low while the ADC is converting.
Minimize the Device Active Time
In systems that have signifi cant time between conversions,
the ADC draws a minimal amount of power. Figures 12
and 13 show two ways to minimize the amount of time
the ADC draws power. In Figure 12, the ADC draws power
during t
the time. The conversion results are available at the next
CONV falling edge. In Figure 13, the ADC draws twice the
power than that in Figure 12, but the conversion results
are available during t
SCK available in the system to shorten data transfer time,
t
SDO Loading
Capacitive loading on the digital output can increase power
consumption. A 100pF capacitor on the SDO pin can add
more than 50μA to the supply current at a 200kHz clock
frequency. An extra 50μA or so of current goes into charg-
ing and discharging the load capacitor. The same goes for
digital lines driven at a high frequency by any logic. The
C • V • f currents must be evaluated with the troublesome
ones minimized.
DATA
LTC2360/LTC2361/LTC2362
+ t
CONV
as long as t
RECOMMENDED HIGH OR LOW
+ t
ACQ
SLEEPMODE
and t
Hi-Z STATE
CONV
4
and t
DATA
SLEEP MODE
and is in sleep mode for the rest of
7
are not violated.
. The user can use the fastest
DD
when it is high.
236012 F12
15
236012f