LTC2400 Linear Technology, LTC2400 Datasheet - Page 18

• Manufacturer Part Number: LTC2400
• Description: 24-Bit uPower No Latency ADC in SO-8
• Manufacturer: Linear Technology

APPLICATIONS
LTC2400
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
(if EOC = 0) or t
during the falling edge of EOC). The value of t
if the device is using its internal oscillator (F
or HIGH). If F
frequency f
HIGH before time t
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
18
(INTERNAL)
SDO
SCK
CS
EOSC
Hi-Z
SLEEP
O
EOCtest
> t
, then t
EOCtest
is driven by an external oscillator of
EOCtest
BIT 0
EOC
U
after EOC goes LOW (if CS is LOW
EOCtest
EOCtest
CONVERSION
Hi-Z
INFORMATION
, the device remains in the sleep
U
DATA OUTPUT
TEST EOC
is 3.6/f
after the falling edge of CS
Figure 9. Internal Serial Clock, Reduced Data Output Length
Hi-Z
EOCtest
W
TEST EOC
EOSC
SLEEP
–0.12V
, the first rising
Hi-Z
. If CS is pulled
EOCtest
0
<t
REF
= logic LOW
EOCtest
BIT 31
0.1V TO V
TO 1.12V
U
EOC
is 23 s
1 F
2.7V TO 5.5V
V
REF
V
REF
CC
IN
BIT 30
V
V
V
GND
CC
REF
IN
LTC2400
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
BIT 29
SIG
SDO
SCK
CS
F
O
DATA OUTPUT
BIT 28
EXR
BIT 27
V
MSB
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
BIT 26
BIT 8
V
CC
10k
CONVERSION
Hi-Z
TEST EOC
2400 F09