LTC2400 Linear Technology, LTC2400 Datasheet - Page 32

• Manufacturer Part Number: LTC2400
• Description: 24-Bit uPower No Latency ADC in SO-8
• Manufacturer: Linear Technology

LTC2400
TYPICAL APPLICATIONS
*
DIN1
DIN2
DIN3
DIN4
*
**********************
* Start GETDATA Routine *
**********************
*
INIT1
*
*
*DDRD's bit 5 is a 1 so that port D's SS* pin is a general output
*
*
*
*
GETDATA PSHX
*
*
TRFLP1 LDAA
*
WAIT1
*
*
*
*
32
EQU
EQU
EQU
EQU
ORG
LDAA
STAA
LDAA
STAA
LDAA
STAA
PSHY
PSHA
LDX
LDY
BCLR
STAA
LDAA
BPL
LDAA
STAA
INX
CPX
BNE
BSET
PULA
PULY
PULX
RTS
LDS
$00
$01
$02
$03
$C000
#$CFFF
#$2F
PORTD
#$38
DDRD
#$50
SPCR
#$0
#$1000
PORTD, Y %00100000
#$0
SPDR
SPSR
WAIT1
SPDR
0,X
#DIN4+1 Has the last byte been transferred/exchanged?
TRFLP1 If the last byte has not been reached, then proceed to the
PORTD,Y %00100000 This sets the SS* output bit to a logic high,
This memory location holds the LTC2400's bits 31 - 24
This memory location holds the LTC2400's bits 23 - 16
This memory location holds the LTC2400's bits 15 - 08
This memory location holds the LTC2400's bits 07 - 00
Program start location
Top of C page RAM, beginning location of stack
–,–,1,0;1,1,1,1
–, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
Keeps SS* a logic high when DDRD, bit 5 is set
–,–,1,1;1,0,0,0
SS*, SCK, MOSI are configured as Outputs
MISO, TxD, RxD are configured as Inputs
The SPI is configured as Master, CPHA = 0, CPOL = 0
and the clock rate is E/2
(This assumes an E-Clock frequency of 4MHz. For higher E-
Clock frequencies, change the above value of $50 to a value
that ensures the SCK frequency is 2MHz or less.)
The X register is used as a pointer to the memory locations
that hold the conversion data
Load accumulator A with a null byte for SPI transfer
This writes the byte in the SPI data register and starts
the transfer
This loop waits for the SPI to complete a serial
transfer/exchange by reading the SPI Status Register
The SPIF (SPI transfer complete flag) bit is the SPSR's MSB
and is set to one at the end of an SPI transfer. The branch
will occur while SPIF is a zero.
Load accumulator A with the current byte of LTC2400 data
that was just received
Transfer the LTC2400's data to memory
Increment the pointer
next byte for transfer/exchange
de-selecting the LTC2400
Restore the A register
Restore the Y register
Restore the X register
Figure 34. This is an Example of 68HC11 Code That Captures the LTC2400’s
Conversion Results Over the SPI Serial Interface Shown in Figure 33
U
This sets the SS* output bit to a logic
low, selecting the LTC2400