LTC2424 Linear Technology, LTC2424 Datasheet - Page 18

• Manufacturer Part Number: LTC2424
• Description: 4-/8-Channel 20-Bit uPower No Latency ADCs
• Manufacturer: Linear Technology

APPLICATIONS
LTC2424/LTC2428
SCK/CLK
signal is used to monitor and control the state of the
conversion cycles as well as enable the channel selection.
The multiplexer is programmed during the data output
state. The internal serial clock (SCK) generated by the ADC
is applied to the multiplexer clock input (CLK).
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (HI-Z) or pulled
HIGH prior to the falling edge of CSADC. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CSADC. An internal weak pull-up
CONVERTER
18
CSADC/
CSMUX
SCK/CLK
SDO
CSADC/
CSMUX
D
STATE
IN
SDO
D
IN
TEST EOC
TEST EOC
CONV
DON’T CARE
Hi-Z
U
TEST EOC
TEST EOC
Figure 15. External Serial Clock with Reduced Data Output Length Timing Diagram
INFORMATION
SLEEP
U
Hi-Z
EN
Figure 14. Use of Look Ahead to Program Multiplexer After Data Output
D2
BIT23
D1
Hi-Z
W
BIT22
D0
DON’T CARE
BIT21
SIG
BIT20
EXR
TO 1.12V
–0.12V
U
BIT19 BIT18
MSB
DATA OUTPUT
TO V
2.7V TO 5.5V
0.1V
REF
REF
CC
BIT23
V
FS
CH0
TO CH7
MUXOUT
ADCIN
ZS
GND
LTC2424/LTC2428
CC
SET
SET
BIT4
BIT22
resistor is active on the SCK pin during the falling edge of
CSADC; therefore, the internal serial clock timing mode is
automatically selected if SCK is not externally driven.
The serial data output pin (SDO) is HI-Z as long as CSADC
is HIGH. At any time during the conversion cycle, CSADC
may be pulled LOW in order to monitor the state of the
converter. Once CSADC is pulled LOW, SCK goes LOW
and EOC is output to the SDO pin. EOC = 1 while a
conversion is in progress and EOC = 0 if the device is in the
sleep state.
BIT21
SIG
CSMUX
CSADC
SDO
SCK
CLK
D
F
BIT20
IN
EXR
O
LSB
BIT0
BIT19 BIT18
MSB
CS
SCK
EN
V
INTERNAL CALIBRATION
CC
D2
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
66ms LOOK AHEAD
DON’T CARE
133ms CONVERSION CYCLE (OUTPUT RATE = 7.5Hz)
D1
BIT9
D0
DON’T CARE
BIT8
CONVERSION ON SELECTED CHANNEL
66ms CONVERT
24248 F14
24248 F15