LTC2498 Linear Technology, LTC2498 Datasheet - Page 23

• Manufacturer Part Number: LTC2498
• Description: 24-Bit 8-/16-Channel ADC
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
ing into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the fall-
ing edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
32nd falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be fl oating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
(EXTERNAL)
SDO
SCK
SDI
CS
CONVERSION
DON'T CARE
SLEEP
BIT 31
1
EOC
1
BIT 30
“0”
0
2
Figure 8. External Serial Clock, 3-Wire Operation (CS = 0)
BIT 29
10μF
SIG
EN
2.7V TO 5.5V
3
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
MSB
SGL
4
0.1V TO V
REFERENCE
0.1μF
ANALOG
INPUTS
VOLTAGE
ODD
5
CC
•
•
•
•
•
•
A2
28
29
30
15
16
23
8
7
6
V
REF
REF
CH0
CH7
CH8
CH15
COM
CC
•
•
•
•
•
•
DATA INPUT/OUTPUT
LTC2498
+
–
A1
7
GND
SDO
SCK
SDI
CS
A0
F
8
O
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must be
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (F
the fi rst rising edge of SCK occurs 12μs (t
after the falling edge of CS. If F
oscillator of frequency f
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 32nd rising edge of SCK a new conversion au-
tomatically begins. SDO goes HIGH (EOC = 1) and SCK
1,3,4,5,6,31,32,33,39
34
38
35
37
36
EN2
9
3-WIRE
SPI INTERFACE
IM
10
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
FA
11
BIT 20 BIT 19
FB
12
SPD
13
EOSC
BIT 18 BIT 17
14
, then t
DON'T CARE
O
is driven by an external
EOCTEST
EOCTEST
LTC2498
, the fi rst rising
EOCTEST
BIT 0
O
32
= 3.6/f
is tied LOW),
CONVERSION
= 12μs)
23
EOSC
2498 F08
2498fc
.