LTC3412A Linear Technology, LTC3412A Datasheet - Page 13

• Manufacturer Part Number: LTC3412A
• Description: 3A/ 4MHz/ Monolithic Synchronous Step-Down Regulator
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the effi ciency and which change would produce
the most improvement. Effi ciency can be expressed as:
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
The V
at very low load currents whereas the I
the effi ciency loss at medium to high load currents. In a
typical effi ciency plot, the effi ciency curve at very low load
currents can be misleading since the actual power lost is
of no consequence.
1. The V
the DC bias current as given in the electrical characteris-
tics and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V
of V
continuous mode, I
QB are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V
nounced at higher supply voltages.
2. I
internal switches, R
tinuous mode the average output current fl owing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
The R
be obtained from the Typical Performance Characteristics
Effi ciency = 100% – (L1 + L2 + L3 + ...)
R
2
IN
SW
R losses are calculated from the resistances of the
IN
DS(ON)
that is typically larger than the DC bias current. In
IN
quiescent current loss dominates the effi ciency loss
= (R
IN
IN
to ground. The resulting dQ/dt is the current out
DS(ON)
quiescent current is due to two components:
quiescent current and I
DS(ON)
for both the top and bottom MOSFETs can
IN
and the duty cycle (DC) as follows:
TOP)(DC) + (R
; thus, their effects will be more pro-
U
GATECHG
SW
, and external inductor R
U
= f(QT + QB) where QT and
DS(ON)
2
W
R losses.
2
R loss dominates
BOT)(1 – DC)
U
L
. In con-
curves. To obtain I
multiply the result by the square of the average output
current.
Other losses including C
and inductor core losses generally account for less than
2% of the total loss.
Thermal Considerations
In most applications, the LTC3412A does not dissipate
much heat due to its high effi ciency.
However, in applications where the LTC3412A is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the part.
If the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3412A from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
where P
is the thermal resistance from the junction of the die to
the ambient temperature. For the 16-lead exposed TSSOP
package, the θ
the θ
The junction temperature, T
where T
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
To maximize the thermal performance of the LTC3412A,
the exposed pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current.
t
T
r
J
= (P
JA
= T
is 34°C/W.
A
D
A
D
is the ambient temperature.
is the power dissipated by the regulator and θ
)(θ
+ t
r
JA
JA
)
is 38°C/W. For the 16-lead QFN package
2
R losses, simply add R
IN
and C
J
, is given by:
OUT
www.DataSheet4U.com
ESR dissipative losses
LTC3412A
SW
to R
DS(ON)
13
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and
JA
).