LTC3553 Linear Technology Corporation, LTC3553 Datasheet - Page 24

• Manufacturer Part Number: LTC3553
• Description: Micropower USB Power Manager
• Manufacturer: Linear Technology Corporation

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LTC3553
OPERATION
(together with the buck regulator). When the STBY pin is
brought high, LDO bias current is reduced. Unlike the buck
regulator, the LDO’s load capability remains unchanged.
However, the LDO’s transient response is slowed, as il-
lustrated in Figure 5 and Figure 6.
V
An undervoltage lockout circuit on the USB PowerPath
V
the LDO from enabling when the V
below about 2.6V.
Buck Regulator UVLO Considerations
It is recommended that the buck regulator input supply
(BVIN pin) be connected directly to the USB PowerPath
output (V
prevents the buck regulator from operating at low input
supply voltages where loss of regulation or other unde-
24
OUT
OUT
Figure 5. LDO Load Step Response in Normal Operation
Figure 6. LDO Load Step Response in Standby Mode
AC-COUPLED
AC-COUPLED
LDO OUTPUT
LDO OUTPUT
UNDERVOLTAGE LOCKOUT (V
pin shuts down and prevents both the buck and
I
I
LDO
LDO
VOLTAGE
VOLTAGE
0.1V/DIV
0.1V/DIV
150mA
150mA
OUT
5mA
5mA
LDO REGULATING 3.3V
4.7μF OUTPUT CAPACITOR
STBY LOW
LDO REGULATING 3.3V
4.7μF OUTPUT CAPACITOR
STBY HIGH
pin). With this connection, the V
50μs/DIV
50μs/DIV
OUT
OUT
pin voltage drops
3553 F05
3553 F06
UVLO)
OUT
UVLO
sirable operation may occur. In applications where the
buck input is supplied from other than the V
measures should be taken to ensure that the buck is not
operated outside the specifi ed BVIN input supply range,
as operation beyond this range is not guaranteed.
LDO Regulator UVLO Considerations
The LDO regulator’s bias current is supplied via an internal
connection to the USB PowerPath V
shuts down the LDO when V
in order to prevent the LDO from operating incorrectly
due to too low a bias supply voltage.
The LDO power input pin, V
little as 1.65V. There is, however, no UVLO to enforce
this requirement. It is thus recommended that V
tied to either the buck regulator output (programmed to
regulate at least 1.65V), or to the USB PowerPath V
pin, to ensure proper operation.
PUSHBUTTON INTERFACE
State Diagram/Operation
Figure 7 shows the LTC3553 pushbutton state diagram.
Upon fi rst application of power, V
nal power on reset (POR) signal places the pushbutton
circuitry into the power-down (PDN1) state. One second
EXTPWR OR
PB400MS
1SEC
Figure 7. Pushbutton State Diagram
PUP2
PDN2
POFF
HRST
EITHER BUCK_ON
OR LDO_ON
UVLO AND
5SEC
HRST
UVLO OR
BOTH BUCK_ON
AND LDO_ON
EXTPWR OR
PB400MS
INLDO
OUT
PDN1
PUP1
PON
HR
drops below about 2.6V
, can be driven with as
OUT
5SEC
HRST
BUS
POR
pin. The V
or BAT, an inter-
BUCK_ON
OR LDO_ON
OUT
3553 F07
OUT
pin, other
INLDO
1SEC
UVLO
OUT
3553f
be