LTC4215 Linear Technology, LTC4215 Datasheet - Page 16

• Manufacturer Part Number: LTC4215
• Description: Hot Swap Controller
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
LTC4215
The inrush dI/dt is set to 10A/ms using C
For a start-up time of 4ms with a 2x safety margin we
choose:
Note the minimum value of C
of soft-start capacitance needs 10nF of TIMER capaci-
tance/time during start-up.
Choose R1, R2, R3, R7 and R8 for the UV, OV and PG
threshold voltages:
V
= 1.235 rising and 1.185V falling)
V
= 1.235V rising and 1.215V falling)
V
= 1.235V rising and 1.155V falling)
A 0.1µF capacitor, C
supply glitches from turning off the GATE via UV or OV.
The address is set with the help of Table 1, which indi-
cates binary address 1010011 corresponds to address
19. Address 19 is set by setting ADR2 high, ADR1 open
and ADR0 high.
Next the value of R5 and R6 are chosen to be the default
values 10Ω and 15k as discussed previously.
In addition a 0.1µF ceramic bypass capacitor is placed
on the INTV
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is required. The minimum trace width for 1oz copper
16
OV(RISING)
UV(RISING)
PG(RISING)
C
C
C
SS
TIMER
TIMER
=
=
10000
dI dt A
10
=
=
= 10.75V, V
= 11.6V, V
= 14.0V, V
CC
/
µA
2
1 1 2 3
I
SS
pin.
•
.
⎛
⎝
12 3
8
t
• • .
ms
ms µF
s
STARTUP
0 0375
U
.
⎞
⎠
F
, is placed on the UV pin to prevent
ms µF
/
PG(FALLING)
• .
OV(FALLING)
UV(FALLING)
0 0375
/
+
U
•
7 5
+
.
5
TIMER
m
C
nF
1
•
SS
Ω
R
= 10.85V (using V
= 13.5V (using V
•
= 10.6V (using V
SENSE
=
•
10 0 68
is 10nF, and each 1nF
W
10
1
7 5
.
≅
nF
SS
.
:
µF
U
OV(TH)
UV(TH)
FB(TH)
foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. Using 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530µΩ/
quickly in high current applications. To improve noise
immunity, put the resistive dividers to the UV, OV and FB
pins close to the device and keep traces to V
short. It is also important to put the bypass capacitor for
the INTV
and GND. A 0.1µF capacitor from the UV pin (and OV pin
through resistor R2) to GND also helps reject supply noise.
Figure 4 shows a layout that addresses these issues. Note
that a surge suppressor, Z1, is placed between supply and
ground using wide traces.
Digital Interface
The LTC4215 communicates with a bus master using a
2-wire interface compatible with I
I
The LTC4215 is a read-write slave device and supports
SMBus bus Read Byte, Write Byte, Read Word and Write
Word commands. The second word in a Read Word com-
mand is identical to the fi rst word. The second word in a
Write Word command is ignored. Data formats for these
commands are shown in Figures 6 to 11.
2
C extension for low power devices.
Z1
CC
pin, C3, as close as possible between INTV
C
SENSE RESISTOR R
F
Figure 5. Recommended Layout
R1
R2
R3
UV
OV
SS
GND
ON
EN
SDAO
S
®
LTC4215UFD
. Small resistances add up
I
LOAD
C3
2
C Bus and SMBus, an
I
LOAD
INTV
TIMER
ADR2
ADR1
GPIO
ADIN
FB
CC
DD
and GND
R8
4215fb
4215 F05
CC