LTC4215 Linear Technology, LTC4215 Datasheet - Page 8

• Manufacturer Part Number: LTC4215
• Description: Hot Swap Controller
• Manufacturer: Linear Technology

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LTC4215
PI FU CTIO S
EXPOSED PAD (Pin 25, QFN Package): Exposed Pad may
be left open or connected to device ground.
FB: Foldback Current Limit and Power Good Input. A
resistive divider from the output is tied to this pin. When
the voltage at this pin drops below 1.235V, power is not
considered good. The power bad condition may result in
the GPIO pin pulling low or going high impedance depend-
ing on the confi guration of control register bits A6 and
A7. Also a power bad fault is logged in this condition if
the LTC4215 has fi nished the start-up cycle and the GATE
pin is high. See Applications Information. The start-up
current limit folds back linearly from 25mV sense voltage
at 0.6V to 10mV at 0.2V on the FB pin. Foldback is not
active once the part leaves start-up and the current limit
is increased to 75mV.
GATE: Gate Drive for External N-Channel MOSFET. An inter-
nal 20µA current source charges the gate of the MOSFET.
No compensation capacitor is required on the GATE pin, but
a resistor and capacitor network from this pin to ground
may be used to set the turn-on output voltage slew rate.
During turn-off there is a 1mA pulldown current. During
a short circuit or undervoltage lockout (V
a 450mA pulldown current source between GATE and
SOURCE is activated.
GND: Device Ground.
GPIO: General Purpose Input/Output. Open-drain logic
output or logic input. Defaults to an output set to pull low to
indicate power is not good. Confi gure according to Table 2.
INTV
a 0.1µF capacitor from this pin to ground.
ON: On Control Input. A rising edge turns on the external
N-channel MOSFET and a falling edge turns it off. This
pin also confi gures the state of the FET On bit in the con-
trol register (and hence the external MOSFET) at power
up. For example, if the ON pin is tied high, then the FET
On bit (A3 in Table 2) goes high 100ms after power-up.
Likewise if the ON pin is tied low then the part remains
off after power-up until the FET On bit is set high using
the I
the fault register.
OV (QFN Package): Overvoltage Comparator Input. Con-
nect this pin to an external resistive divider from V
8
U
2
CC
C bus. A high-to-low transition on this pin clears
: Low Voltage Supply Decoupling Output. Connect
U
U
DD
or INTV
DD
. If the
CC
),
voltage at this pin rises above 1.235V, an overvoltage fault
is detected and the GATE turns off. Tie to GND if unused.
SCL: Serial Bus Clock Input. Data at the SDA pin is shifted
in or out on rising edges of SCL. This is a high impedance
pin that is generally driven by an open-collector output
from a master controller. An external pull-up resistor or
current source is required.
SDAO (QFN Package): Serial Bus Data Output. Open-drain
output for sending data back to the master controller or
acknowledging a write operation. Normally tied to SDAI
to form the SDA line. An external pull-up resistor or cur-
rent source is required. Internally tied to SDAI in SSOP
package.
SDAI: Serial Bus Data Input. A high impedance input for
shifting in address, command or data bits. Normally tied
to SDAO to form the SDA line. Internally tied to SDAO in
SSOP package.
SDA (SSOP Package): Serial Bus Data Input/Output Line.
Formed by internally tying the SDAO and SDAI lines to-
gether. An external pull-up resistor or current source is
required.
SENSE
Connect this pin to the input of the current sense resistor.
Must be connected to the same trace as V
tied to V
SENSE
to the output of the current sense resistor. The current
limit circuit controls the GATE pin to limit the sense voltage
between the SENSE and V
SOURCE: N-Channel MOSFET Source and ADC Input.
Connect this pin to the source of the external N-channel
MOSFET switch for gate drive return. This pin also serves as
the ADC input to monitor output voltage. The pin provides
a return for the gate pulldown circuit.
SS: Sets the inrush current slew rate at start-up. Connect
a 68nF capacitor to provide 5mV/ms as the slew rate for
the sense voltage in start-up. This corresponds to 1A/ms
with a 5mΩ sense resistor. Note that a large soft-start
capacitor and a small TIMER capacitor may result in a
condition where the timer expires before the inrush current
has started. Allow an additional 10nF of timer capacitance
+
–
: Negative Current Sense Input. Connect this pin
DD
(QFN Package): Positive Current Sense Input.
in SSOP package.
DD
pins to 25mV or less.
DD
. Internally
4215fb