LTC4222 Linear Technology, LTC4222 Datasheet - Page 12

• Manufacturer Part Number: LTC4222
• Description: Dual Hot Swap Controller
• Manufacturer: Linear Technology

www.DataSheet4U.com
LTC4222
TIMING DIAGRAM
OPERATION
The LTC4222 is designed to turn two supply voltages
on and off in a controlled manner, allowing boards to be
safely inserted or removed from a live backplane. During
normal operation, the charge pump and gate drivers turn
on external N-channel MOSFET gates to pass power to
the loads. The gate driver circuits use a charge pump that
derives its power from the V
higher. Also included in the gate driver circuits are internal
6.5V GATE to SOURCE clamps to protect the oxide of
logic level MOSFETs. During start-up the inrush currents
are tightly controlled by using current limit foldback, soft
start dI/dt limiting and output dI/dt limiting. The LTC4222
is capable of controlling both channels independently, or
coupling control signals so that both channels start up
and turn off together.
The current sense (CS) amplifi ers monitor the load cur-
rents using the difference between the SENSE+ (V
QFN) and SENSE
current in the load by pulling back on the GATE-to-SOURCE
voltage in an active control loop when the sense voltage
exceeds the commanded value. The CS amplifi ers require
20μA input bias current from both the SENSE
SENSE
A short circuit on an output to ground results in excessive
power dissipation during active current limiting. To limit this
power, the corresponding CS amplifi er regulates the voltage
between the SENSE+ and SENSE– pins at 150mV.
If an overcurrent condition persists, the internal circuit
breaker (CB) registers a fault when the sense voltage
exceeds 50mV for more than 20μs. This indicates to
the logic that it is time to turn off the GATE to prevent
12
–
pins.
SDAI/SDAO
t
SCL
HD, STA
–
pin voltages. A CS amplifi er limits the
CONDITION
START
DD1
or V
t
SU, DAT
DD2
pin, whichever is
t
t
HD, DATO,
HD, DATI
+
and the
DD
for
REPEATED START
CONDITION
overheating. At this point the TIMER capacitor starts to
discharge with the 2μA current source until the voltage
drops below 0.2V (comparator TM1) which tells the logic
that the pass transistor has cooled and it is safe to turn
on again if overcurrent auto-retry is enabled. If the TIMER
pin is tied to INTV
seconds using an internal system timer.
The output voltages are monitored using the FB resistive
divider and the Power Good (PG) comparators to determine
when output voltages are acceptable for the loads. The
power good conditions are signaled by the GPIO1 and
GPIO2 pins using open-drain pull-down transistors. The
GPIO pins may also be independently confi gured to signal
power bad, or as general purpose inputs (GP comparators),
or general purpose open drain outputs.
The Functional Diagram shows the monitoring blocks of
the LTC4222. The group of comparators on the left side
includes the undervoltage (UV), overvoltage (OV), reset
(RST), enable (EN) and on (ON) comparators for chan-
nel 1 or 2. These comparators determine if the external
conditions are valid prior to turning on their correspond-
ing GATE. The two undervoltage lockout circuits, UVLO1
and UVLO2, validate the input supplies and the internally
generated 3.3V supply, INTV
the power-up initialization to the logic circuits as INTV
crosses this rising threshold.
The CONFIG pin is used to select the desired startup be-
havior of the LTC4222. When the CONFIG pin is low, both
channels will start up and turn off simultaneously and a
fault on either channel will result in both channels turning
off, or prevent both channels from starting up. When the
t
SU, STA
t
HD, STA
t
SP
t
SP
t
SU, STO
CC
, the cool-down time defaults to 5
CONDITION
STOP
CC
t
. UVLO2 also generates
BUF
CONDITION
START
4222 TD01
4222f
CC