LTC4222 Linear Technology, LTC4222 Datasheet - Page 21

• Manufacturer Part Number: LTC4222
• Description: Dual Hot Swap Controller
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
The address is set with the help of Table 1, which indi-
cates binary address 1000111 corresponds to address
4. Address 4 is set by setting ADR2 low, ADR1 open and
ADR0 high.
Next the value of R5 and R6 are chosen to be the default
values 10Ω and 15kΩ as discussed previously.
In addition a 0.1μF ceramic bypass capacitor is placed on
the INTV
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is required. The minimum trace width for 1oz copper
foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. Using 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530μΩ. Small resistances add up
quickly in high current applications. To improve noise
immunity, put the resistive dividers to the UV, OV and FB
pins close to the device and keep traces to V
short. It is also important to put the bypass capacitor for
the INTV
and GND. 0.1μF capacitors from the UV pins (and OV pins
through resistor R2) to GND also helps reject supply noise.
Figure 5 shows a layout that addresses these issues. Note
that surge suppressor, Z1 is placed between supply and
ground using wide traces.
GROUND
VIAS TO
PLANE
Z1
GROUND
CC
CC
VIA TO
PLANE
pin, C3, as close as possible between INTV
pin.
Figure 5. Recommended Layout
C
C3
SS
C
F
SS
CONFIG
INTV
GND
R3
R1
CC
R2
LTC4222UHD
SENSE RESISTOR R
DD
S
and GND
I
LOAD
4222 F05
CC
Digital Interface
The LTC4222 communicates with a bus master using a
2-wire interface compatible with I
I
read-write slave device and supports SMBus bus Read
Byte, Write Byte, Read Word and Write Word commands.
A complete list of the resistors of the LTC4222 is shown
in Table 2. The second word in a Read Word command is
the contents of the subsequent 8 bit register. The second
word in a Write Word command is ignored. Data formats
for these commands are shown in Figures 6 to 11.
The LTC4222 interface also features a 25ms timeout feature
to prevent the bus being stuck low if a communication
error occurs. If either the SCL or SDA lines remain low
for more than 25ms the LTC4222 will reset it’s interface
and release the SDAO pin, freeing the bus to resume
communication.
The LTC4222 also features PMBus compatibility, the in-
terface will not acknowledge unsupported commands and
the internal addresses are in the manufacturer specifi ed
address space under the PMBus specifi cation.
START and STOP Conditions
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a start
condition by transitioning SDA from high to low while SCL
is high, as shown in Figure 6. When the master has fi nished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
I
Twenty seven distinct bus addresses are available using
three 3-state address pins, ADR0, ADR1 and ADR2. Table
1 shows the correspondence between pin states and ad-
dresses. In addition, the LTC4222 responds to two special
addresses. Address (1100 0110) is a mass write address
that writes to all LTC4222s, regardless of their individual
address settings. Mass write can be disabled by setting
register bit 4 in the CONTROL register of channel 2 to zero.
Address (0001 100) is the SMBus Alert Response Address.
If the LTC4222 is pulling low on the ALERT pin due to an
2
2
C extension for low power devices. The LTC4222 is a
C Device Addressing
2
C Bus and SMBus, an
LTC4222
21
4222f