LTC4278 Linear Technology, LTC4278 Datasheet - Page 22

• Manufacturer Part Number: LTC4278
• Description: IEEE 802.3at PD
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
LTC4278
compensation circuitry. The logic block also contains
circuitry to control the special dynamic requirements of
fl yback control. For more information on the basics of
current mode switcher/controllers and isolated fl yback
converters see Application Note 19.
Feedback Amplifi er—Pseudo DC Theory
For the following discussion, refer to the simplifi ed
Switching Regulator Feedback Amplifi er diagram (Figure
10A). When the primary-side MOSFET switch MP turns off,
its drain voltage rises above the V
when the primary MOSFET is off and the synchronous
secondary MOSFET is on. During fl yback the voltage on
nondriven transformer pins is determined by the secondary
voltage. The amplitude of this fl yback pulse, as seen on
the third winding, is given as:
R
I
ESR = impedance of secondary circuit capacitor, winding
and traces
N
turns ratio (i.e., N
The fl yback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
amplifi er compares the voltage to the internal bandgap
reference. The feedback amp is actually a transconductance
amplifi er whose output is connected to V
a period in the fl yback time. An external capacitor on
the V
provide the control voltage to set the current mode trip
point. The regulation voltage at the FB pin is nearly equal
to the bandgap reference V
the overall loop. The relationship between V
is expressed as:
22
SEC
DS(ON)
SF
V
V
= transformer effective secondary-to-fl yback winding
FLBK
FLBK
= transformer secondary current
CMP
= on-resistance of the synchronous MOSFET MS
=
=
pin integrates the net feedback amp current to
R
V
OUT
+ 1 2
R
2
R
+
I
SEC
S
•
/N
V
FB
FLBK
•
N
(
ESR R
SF
)
FB
+
because of the high gain in
DS ON
PORTP
(
)
)
rail. Flyback occurs
CMP
FLBK
only during
and V
FB
Combining this with the previous V
an expression for V
programming resistors and secondary resistances:
The effect of nonzero secondary output impedance is
discussed in further detail (see Load Compensation
Theory). The practical aspects of applying this equation for
V
Information.
Feedback Amplifi er Dynamic Theory
So far, this has been a pseudo-DC treatment of fl yback
feedback amplifi er operation. But the fl yback signal is a
pulse, not a DC level. Provision is made to turn on the
fl yback amplifi er only when the fl yback pulse is present,
using the enable signal as shown in the timing diagram
(Figure 10b).
Minimum Output Switch On Time (t
The LTC4278 affects output voltage regulation via fl yback
pulse action. If the output switch is not turned on, there
is no fl yback pulse and output voltage information is
not available. This causes irregular loop response and
start-up/latchup problems. The solution is to require the
primary switch to be on for an absolute minimum time per
each oscillator cycle. To accomplish this the current limit
feedback is blanked each cycle for t
is less than that developed under these conditions, forced
continuous operation normally occurs. See subsequent
discussions in the Applications Information section for
further details.
Enable Delay Time (ENDLY)
The fl yback pulse appears when the primary-side switch
shuts off. However, it takes a fi nite time until the transformer
primary-side voltage waveform represents the output
voltage. This is partly due to rise time on the primary-
side MOSFET drain node, but, more importantly, is due
OUT
V
OUT
are found in subsequent sections of the Applications
=
R1+R2
R2
OUT
• V
FB
in terms of the internal reference,
• N
SF
ON(MIN)
I
SEC
FLBK
ON(MIN)
• ESR+R
expression yields
(
. If the output load
)
DS(ON)
4278f
)