LTC4278 Linear Technology, LTC4278 Datasheet - Page 33

• Manufacturer Part Number: LTC4278
• Description: IEEE 802.3at PD
• Manufacturer: Linear Technology

www.DataSheet4U.com
APPLICATIONS INFORMATION
In further contrast to traditional current mode switchers,
V
The dynamic nature of the clamped feedback amplifi er
forms an effective track/hold type response, whereby the
V
held during the subsequent switch-on portion of the next
cycle. This action naturally holds the V
during the current comparator sense action (current mode
switching).
Application Note 19 provides a method for empirically
tweaking frequency compensation. Basically, it involves
introducing a load current step and monitoring the
response.
Slope Compensation
The LTC4278 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stability when the DC is greater than 50%. In some switching
regulators, slope compensation reduces the maximum peak
current at higher duty cycles. The LTC4278 eliminates this
problem by having circuitry that compensates for the slope
compensation so that maximum current sense voltage is
constant across all duty cycles.
Minimum Load Considerations
At light loads, the LTC4278 derived regulator goes into
forced continuous conduction mode. The primary-side
switch always turns on for a short time as set by the
t
load requires, power will fl ow back into the primary dur-
ing the off period when the synchronization switch is on.
This does not produce any inherently adverse problems,
although light load effi ciency is reduced.
Maximum Load Considerations
The current mode control uses the V
and amplifi ed sense resistor voltage as inputs to the
current comparator. When the amplifi ed sense voltage
exceeds the V
is turned off.
ON(MIN)
CMP
CMP
pin ripple is generally not an issue with the LTC4269-1.
voltage changes during the fl yback pulse, but is then
resistor. If this produces more power than the
CMP
node voltage, the primary-side switch
CMP
CMP
voltage stable
node voltage
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
V
MOSFET will turn off at the rated 100mV V
repeats on the next cycle.
It is possible for the peak primary switch currents as
referred across R
because of the minimum switch on time blanking. If the
voltage on V
turn-on time, the SFST capacitor is discharged, causing
the discharge of the V
the peak current on the next cycle and will reduce overall
stress in the primary switch.
Short-Circuit Conditions
Loss of current limit is possible under certain conditions
such as an output short-circuit. If the duty cycle exhibited
by the minimum on-time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is:
where:
Trouble is typically encountered only in applications with
a relatively high product of input voltage times secondary
to primary turns ratio and/or a relatively long minimum
switch on time. Additionally, several real world effects such
as transformer leakage inductance, AC winding losses and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction.
CMP
t
I
N
(other variables as previously defi ned)
DC
ON(MIN)
SC
SP
reaches its 2.56V clamp. At clamp, the primary-side
MIN
is the short-circuit output current
is the secondary-to-primary turns ratio (N
=
is the primary-side switch minimum on-time
t
ON MIN
SENSE
(
SENSE
)
exceeds 205mV after the minimum
•
f
OSC
CMP
to exceed the max 100mV rating
<
capacitor. This then reduces
I
SC
•
(
R
V
SEC
IN
•
LTC4278
+
N
SENSE
R
S S P
DS ON
(
level. This
SEC
)
33
)
/N
PRI
4278f
)