RM5231A PMC-Sierra Inc, RM5231A Datasheet - Page 22

• Manufacturer Part Number: RM5231A
• Description: 64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
3.21 System Interface
3.22 System Address/Data Bus
3.23 System Command Bus
significantly increases performance by decoupling the SysAD bus transfers from the instruction
execution stream.
The system interface consists of a 32-bit Address/Data bus with 4 parity check bits and a 9-bit
command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is
capable of transferring data between the processor and memory at a peak rate of 400 MB/sec with
a 100 MHz SysClock.
Figure 6 shows a typical embedded system using the RM5231A. In this example, a bank of
DRAMs and a memory controller ASIC share the processor’s SysAD bus while the memory
controller provides separate ports to a boot ROM and an I/O system.
Figure 6 Typical Embedded System Block Diagram
The 32-bit System Address Data (SysAD) bus is used to transfer addresses and data between the
RM5231A and the rest of the system. It is protected with a 4-bit parity check bus (SysADC).
The system interface is configurable to allow easy interfacing to memory and I/O systems of
varying frequencies. The Block Write data rate, Non-blocking Write protocol, and the Output
Drive strength are programmable at Boot time via the Mode Control bits. The rate at which the
processor receives data is also fully controlled by the external device.
The RM5231A interface has a 9-bit System Command (SysCmd) bus. The command bus
indicates whether the SysAD bus carries address or data information on a per- clock basis. If the
SysAD carries address, then the SysCmd bus also indicates what type of transaction is to take
place (for example, a read or write). If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data word transmitted, or the data contains
an error). The SysCmd bus is bidirectional to support both processor requests and external
requests to the RM5231A. Processor requests are initiated by the RM5231A and responded to by
an external device. External requests are issued by an external device and require the RM5231A to
respond.
RM5231A
DRAM
Latch
36
36
23
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Control
Address
Memory I/O
Controller
Flash/
Boot
Rom
8
x
PCI Bus
Preliminary
x
22