RM5231A PMC-Sierra Inc, RM5231A Datasheet - Page 5

• Manufacturer Part Number: RM5231A
• Description: 64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
Table of Contents
Legal Information ...........................................................................................................................2
Revision History .............................................................................................................................3
Document Conventions .................................................................................................................4
Table of Contents ..........................................................................................................................5
List of Figures ................................................................................................................................7
List of Tables .................................................................................................................................8
1
2
3
Features ..................................................................................................................................9
Block Diagram .......................................................................................................................10
Hardware Overview ...............................................................................................................11
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10 Floating-Point General Register File ............................................................................15
3.11 System Control Coprocessor (CP0) .............................................................................16
3.12 System Control Co-Processor Registers .....................................................................16
3.13 Virtual to Physical Address Mapping ............................................................................17
3.14 Joint TLB ......................................................................................................................18
3.15 Instruction TLB .............................................................................................................19
3.16 Data TLB ......................................................................................................................19
3.17 Cache Memory .............................................................................................................19
3.18 Instruction Cache .........................................................................................................19
3.19 Data Cache ..................................................................................................................20
3.20 Write Buffer ..................................................................................................................21
3.21 System Interface ..........................................................................................................22
3.22 System Address/Data Bus ...........................................................................................22
3.23 System Command Bus ................................................................................................22
3.24 Handshake Signals ......................................................................................................23
3.25 Non-overlapping System Interface ...............................................................................23
3.26 Enhanced Write Modes ................................................................................................24
3.27 External Requests ........................................................................................................25
3.28 Interrupt Handling ........................................................................................................25
3.29 Standby Mode ..............................................................................................................25
3.30 JTAG Interface .............................................................................................................25
Superscalar Dispatch ...................................................................................................11
CPU Registers .............................................................................................................11
Pipeline ........................................................................................................................11
Integer Unit ..................................................................................................................12
Register File .................................................................................................................12
ALU ..............................................................................................................................12
Integer Multiply/Divide ..................................................................................................12
Floating-Point Co-Processor ........................................................................................13
Floating-Point Unit .......................................................................................................13
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
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