FS6377-01g ON Semiconductor, FS6377-01g Datasheet - Page 4

• Manufacturer Part Number: FS6377-01g
• Description: Programmable 3-PLL Clock Generator IC
• Manufacturer: ON Semiconductor

AMI Semiconductor
www.amis.com
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
M-Counter:
FBKDIV[10:3]
00000001
00000010
00000011
00000100
00000101
00000110
00000111
3.1.3 Feedback Divider Programming
Table 2. Feedback Divider Modulus Under 56
3.2 Post Divider Muxes
As shown in Figure 2, an input mux in front of each post
divider stage can select from any one of the PLL
frequencies or the reference frequency. The frequency se-
lection is done via the I
3.3 Post Dividers
The post divider performs several useful functions. First, it
allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it changes
the basic PLL equation to
where N
The FS6377 powers up with all internal registers cleared to
zero, delivering the crystal frequency to all outputs. For
operation to occur, the registers must be loaded in a most-
significant-bit (MSB) to least-significant-bit (LSB) order.
The register mapping of the FS6377 is shown in Table 3,
and I
5.0.
For proper operation of the feedback divider, the A-counter
must be programmed only for values that are less than or
equal to the M-counter. Therefore, not all divider moduli
below 56 are available for use. The selection of divider
4.0 Device Operation
f
2
C-bus programming information is detailed in Section
CLK
F
, N
=
R
and N
f
REF
000
8
16
24
32
40
48
56
P
( )( )
are the feedback, reference and post
2
001
9
17
25
33
41
49
57
C-bus.
N
N
F
R
Feedback Divider Modulus
010
18
26
34
42
50
58
A-Counter: FBKDIV[2:0]
N
011
27
35
43
51
59
1
P
100
36
44
52
60
101
45
53
61
110
54
62
4
111
63
values is listed in Table 2.
Above a modulus of 56, the feedback divider can be
programmed to any value up to 2047.
The input frequency on two of the four muxes (mux C and
D in Figure 2) can be changed without reprogramming by
a logic-level input on the SEL_CD pin.
divider moduli respectively, and f
and reference oscillator frequencies. The extra integer in
the
programming of the loop for many applications where
frequencies must be achieved exactly.
The modulus on two of the four post dividers muxes (post
dividers C and D in Figure 2) can be altered without
reprogramming by a logic level on the SEL_CD pin.
Control of the reference, feedback and post dividers is
detailed in Table 5. Selection of these dividers directly
controls how fast the VCO will run. The maximum VCO
speed is noted in Table 13.
denominator
permits
more
CLK
and f
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flexibility
REF
are the output
in
Data Sheet
the