FS6377-01g ON Semiconductor, FS6377-01g Datasheet - Page 9

• Manufacturer Part Number: FS6377-01g
• Description: Programmable 3-PLL Clock Generator IC
• Manufacturer: ON Semiconductor

AMI Semiconductor
www.amis.com
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Table 3. Register Map
ADDRESS
BYTE 15
BYTE 14
BYTE 13
BYTE 12
BYTE 11
BYTE 10
BYTE 9
BYTE 8
BYTE 7
BYTE 6
BYTE 5
BYTE 4
BYTE 3
BYTE 2
BYTE 1
BYTE 0
(Note: All register bits are cleared to zero on power-up)
6.1 Control Bit Assignment
If any PLL control bit is altered during device operation,
including those bits controlling the reference and feedback
dividers, the output frequency will slew smoothly (in a
glitch-free manner) to the new frequency. The slew rate is
related to the programmed loop filter time constant.
6.1.1 Power Down
All power-down functions are controlled by enable bits.
The bits select which portions of the device to power-down
when the PD input is asserted.
6.0 Programming Information
(selected via SEL_CD = 1)
(selected via SEL_CD = 0)
(selected via SEL_CD = 0)
BIT 7
MUX_D2[1:0]
MUX_D1[1:0]
MUX_C1[1:0]
MUX_B[1:0]
MUX_A[1:0]
(selected via SEL_CD = 1)
(selected via SEL_CD = 0)
BIT 6
(selected via SEL_CD pin = 1)
POST_D2[3:0]
POST_D1[3:0]
POST_B[3:0]
FBKDIV_C2[7:3] M-Counter
FBKDIV_C1[7:3] M-Counter
FBKDIV_B[7:3] M-Counter
FBKDIV_A[7:3] M-Counter
(selected via SEL_CD = 0)
Reserved (0)
(selected via SEL_CD = 1)
PDPLL_C
PDPLL_B
PDPLL_A
BIT 5
MUX_C2[1:0]
(selected via SEL_CD pin = 1)
(SEL_CD=1)
(SEL_CD=0)
(selected via SEL_CD = 0)
LFTC_C2
LFTC_C1
LFTC_B
LFTC_A
BIT 4
9
REFDIV_C2[7:0]
REFDIV_C1[7:0]
REFDIV_B[7:0]
REFDIV_A[7:0]
However, any programming changes to any mux or post
divider control bits will cause a glitch on an operating clock
output.
(SEL_CD=1)
(SEL_CD=0)
PDPOST_D
CP_C2
CP_C1
CP_B
CP_A
BIT 3
PDPOST_C
(selected via SEL_CD = 1)
(selected via SEL_CD = 0)
BIT 2
(selected via SEL_CD pin = 1)
(selected via SEL_CD pin =
POST_C2[3:0]
POST_C1[3:0]
FBKDIV_D2[10:8] M-Counter
FBKDIV_C1[10:8] M-Counter
POST_A[3:0]
FBKDIV_C2[2:0] A-Counter
FBKDIV_C1[2:0] A-Counter
FBKDIV_B[10:8] M-Counter
FBKDIV_A[10:8] M-Counter
FBKDIV_B[2:0] A-Counter
FBKDIV_A[2:0] A-Counter
(selected via SEL_CD = 0)
(selected via SEL_CD = 1)
PDPOST_B PDPOST_A
BIT 1
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BIT 0
1)
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