MBM29DL34TF Fujitsu Media Devices, MBM29DL34TF Datasheet - Page 26

• Manufacturer Part Number: MBM29DL34TF
• Description: (MBM29DL34BF/TF) FLASH MEMORY CMOS 32 M (4 M X 8/2 M X 16) BIT
• Manufacturer: Fujitsu Media Devices

26
MBM29DL34TF/BF
9. Temporary Sector Group Unprotection
10. Hardware RESET
11. Byte/Word Configuration
12. Boot Block Sector Protection
with CE and OE at V
and A
sector. Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses,
except for A
manufacturer and device codes. A
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02h, where the higher order addresses (A
A
sector group. See “MBM29DL34TF/BF Sector Group Protection Verify Autoselect Codes Tables” and
“MBM29DL34TF/BF Extended Autoselect Code Tables” in
This feature allows temporary unprotection of previously protected sector groups of the devices in order to change
data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (V
this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad-
dresses. Once the V
protected again. Refer to “16. Temporary Sector Group Unprotection Timing Diagram” in
and “6. Temporary Sector Group Unprotection Algorithm” in
The devices may be reset by driving the RESET pin to V
and has to be kept low (V
in the process of being executed will be terminated and the internal state machine will be reset to the read mode
“t
additional “t
mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during
a program or erase operation, the data at that particular location will be corrupted.
Please note that the RY/BY output signal should be ignored during the RESET pulse. See “11. RESET, RY/BY
Timing Diagram” in
tection” for additional functionality.
The BYTE pin selects the Byte (8-bit) mode or Word (16-bit) mode for the MBM29DL34TF/BF devices. When
this pin is driven high, the devices operate in the Word (16-bit) mode. The data is read and programmed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to “12. Timing Diagram for Word Mode Configuration”, “13. Timing Diagram for Byte Mode Configuration” and
“14. BYTE Timing Diagram for Write Operations” in
The Write Protection function provides a hardware method of protecting certain boot sectors without using V
This function is one of two provided by the WP/ACC pin.
If the system asserts V
“outermost” 8 K byte boot sectors independently of whether those sectors were protected or unprotected using
the method described in “Sector Group Protection”. The two outermost 8 K byte boot sectors are the two sectors
containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest
addresses in a top-boot-configured device.
If the system asserts V
sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two
(MBM29DL34TF : SA69 and SA70, MBM29DL34BF : SA0 and SA1)
READY
17
, A
16
12
15
” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an
) while (A
, A
. When this pin is driven low, the devices operate in Byte (8-bit) mode. Under this mode, the DQ
15
, A
RH
6
, A
” before it will allow read access. When the RESET pin is low, the devices will be in the standby
14
1
, A
, and A
6
, A
13
, and A
3
, A
IL
ID
and WE at V
TIMING DIAGRAM for the timing diagram. Refer to “9. Temporary Sector Group Unpro-
2
is taken away from the RESET pin, all the previously protected sector groups will be
0
IH
, A
IL
can be either High or Low. Address locations with A
IL
on the WP/ACC pin, the device reverts to whether the two outermost 8 K byte boot
on the WP/ACC pin, the device disables program and erase functions in the two
1
12
) for at least “t
, A
) are the desired sector group address will produce a logic “1” at DQ
0
)
-1
(0, 0, 0, 1, 0) will produce a logic “1” code at device output DQ
IH
requires to apply to V
. Scanning the sector group addresses (A
70
8
RP
to DQ
” in order to properly reset the internal state machine. Any operation
14
bits are tri-stated. However, the command bus cycle is always
TIMING DIAGRAM for the timing diagram.
IL
IL
0
on Byte mode.
from V
to DQ
DEVICE BUS OPERATION for Autoselect codes.
FLOW CHART.
7
IH
and the DQ
. The RESET pin has a pulse requirement
1
20
8
, A
V
to DQ
IL
19
are reserved for Autoselect
, A
15
18
bits are ignored. Refer
, A
17
TIMING DIAGRAM
, A
0
0
16
for a protected
for a protected
, A
20
ID
15
, A
) . During
, A
15
/A
19
14
, A
, A
-1
pin
13
18
ID
0
,
,
.