MBM29SL800BE Fujitsu Media Devices, MBM29SL800BE Datasheet - Page 20

• Manufacturer Part Number: MBM29SL800BE
• Description: (MBM29SL800TE/BE) FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT
• Manufacturer: Fujitsu Media Devices

20
MBM29SL800TE/BE
DQ
Toggle Bit I
DQ
Exceeded Timing Limits
DQ
Sector Erase Timer
See “Data Polling during Embedded Algorithm Operation Timing Diagram” in TIMING DIAGRAM for the Data
Polling timing specifications and diagrams.
The MBM29SL800TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ
cycle is completed, DQ
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 s and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
cause the DQ
See “AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” in
Toggle Bit I timing specifications and diagrams.
DQ
these conditions DQ
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA) .
The OE and WE pins will control the output disable functions as described in “MBM29SL800TE/BE User Bus
Operations (BYTE
OPERATION.
The DQ
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
DQ
used. If this occurs, reset the device with command sequence.
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
be used to determine if the sector erase timer window is still open. If DQ
erase cycle has begun. If DQ
the command has been accepted, the system software should check the status of DQ
each subsequent Sector Erase command. If DQ
have been accepted.
See “Hardware Sequence Flags”.
6
5
3
5
5
bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
6
to toggle.
5
V
will produce a “1”. This is a failure condition which indicates that the program or erase
IH
6
) ” and “MBM29SL800TE/BE User Bus Operations (BYTE
will stop toggling and valid data will be read on the next successive attempts. During
7
bit and DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
3
is low (“0”) the device will accept additional sector erase commands. To insure
6
never stops toggling. Once the devices have exceeded timing limits, the
-90/10
6
to toggle. In addition, an Erase Suspend/Resume command will
3
were high on the second status check, the command may not
3
is high (“1”) the internally controlled
TIMING DIAGRAM for the
V
3
IL
) ” in
prior to and following
DEVICE BUS
3
3
may
will