N74F273AD,602 NXP Semiconductors, N74F273AD,602 Datasheet - Page 2

• Manufacturer Part Number: N74F273AD,602
• Description: IC FLIP FLOP TRI-ST OCTAL 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74Fr
• Type: D-Type Busr

Specifications of N74F273AD,602

• Function: Master Reset
• Output Type: Non-Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 170MHz
• Delay Time - Propagation: 7ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 1mA, 20mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Logic Family: F
• Technology: Bipolar
• Number Of Bits: 8
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Non-Inverting
• Operating Supply Voltage (typ): 5V
• Package Type: SO
• Propagation Delay Time: 10ns
• Low Level Output Current: 20mA
• High Level Output Current: -1mA
• Frequency (max): 125MHz
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935053560602; N74F273AD; N74F273AD

Philips Semiconductors
FEATURES
DESCRIPTION
The 74F273 has eight edge–triggered D–type flip–flops with
individual D inputs and Q outputs. The common buffered Clock (CP)
and Master Reset (MR) inputs load and reset (clear) all flip–flops
simultaneously.
The register is fully edge–triggered. The state of each D input, one
setup time before the Low–to–High clock transition, is transferred to
the corresponding flip–flop’s Q output.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PIN CONFIGURATION
1996 Mar 12
High impedance inputs for reduced loading
(20 A in Low and High states)
Ideal buffer for MOS microprocessor or memory
Eight edge–triggered D–type flip–flops
Buffered common clock
Buffered asynchronous Master Reset
See 74F377A for clock enable version
See 74F373 for transparent latch version
See 74F374 for 3–State version
Octal D flip–flop
Q0 – Q7
D0 – D7
PINS
MR
CP
GND
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Data inputs
Master Reset input (active–Low)
Clock pulse input (active rising edge)
Data outputs
10
1
2
3
4
5
6
7
8
9
SF00346
20
19
18
17
16
15
14
13
12
11
V
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
CC
DESCRIPTION
2
All outputs will be forced Low independently of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where the true output only is required and the CP and
MR are common to all elements.
ORDERING INFORMATION
LOGIC SYMBOL
74F273A
20–pin plastic SOL
20–pin plastic DIP
V
GND = Pin 10
TYPE
CC
PACKAGES
= Pin 20
11
1
TYPICAL
170MHz
CP
MR
f
MAX
D0
Q0
2
3
HIGH/LOW
74F(U.L.)
1.0/0.033
1.0/0.033
1.0/0.033
COMMERCIAL RANGE
D1
Q1
50/33
4
5
T
amb
V
D2
Q2
7
6
CC
74F273AN
74F273AD
= 0 C to +70 C
D3
Q3
TYPICAL SUPPLY CURRENT
= 5V 10%;
8
9
D4
Q4
13
12
D5
Q5
14
15
(TOTAL)
Product specification
D6
Q6
25mA
17
16
LOAD VALUE
SF00347
1.0mA/20mA
74F273A
HIGH/LOW
20 A/20 A
20 A/20 A
20 A/20 A
853–0066 16555
D7
Q7
18
19
PKG. DWG. #
SOT146-1
SOT163-1