cy2dp3120 Cypress Semiconductor Corporation., cy2dp3120 Datasheet - Page 5

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cy2dp3120

Manufacturer Part Number
cy2dp3120
Description
1 20 Differential Clock/data Fanout Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Document #: 38-07514 Rev.*C
Timing Definitions
Figure 4. Propagation Delay (T
A n o t h e r
O u t p u t
O u t p u t
C l o c k
C l o c k
C l o c k
I n p u t
V E E
V E E
V IH
V C C
V C C
V I L
V I H
V I L
V D I F
2 0 - 8 0 %
for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
V P P
t r , t f ,
T P L H ,
T P D
Figure 2. HSTL Differential Input Waveform Definitions
V P P r a n g e
0 .1 V - 1 .3 V
V D I F =
0 . 4 V m i n
Figure 1. PECL/ECL Input Waveform Definitions
PD
> =
), output pulse skew (|t
V E E = 0 . 0 V
Figure 3. ECL/LVPECL Output
V C C = 3 . 3 V
V C M R M in = V E E + 1 . 2
T P H L
PLH
V C M R M a x = V C C
-t
PHL
V X m a x = 0 . 9 V
V X M i n = 0 . 6 8
|), and output-to-output skew (t
t S K ( O )
V P P
V C M R
V O
V O
FastEdge™ Series
V X
CY2DP3120
SK(O)
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