cy29772 Cypress Semiconductor Corporation., cy29772 Datasheet - Page 2

• Manufacturer Part Number: cy29772
• Description: 2.5v Or 3.3v, 200-mhz, 12-output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07572 Rev. *A
Pin Description
11
12
9
10
44, 46, 48, 50 QA(3:0)
32, 34, 36, 38 QB(3:0)
16, 18, 21, 23 QC(3:0)
29
31
25
6
2
8
7
52
14
5, 26, 27
42, 43
40, 41
19, 20
3
4
45, 49
33, 37
22, 17
13
28
1
15, 24, 30, 35,
39, 47, 51
Notes:
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Pin
XIN
XOUT
TCLK0
TCLK1
FB_OUT
FB_IN
SYNC
PLL_EN
MR#/OE
TCLK_SEL
REF_SEL
VCO_SEL
INV_CLK
FB_SEL(2:0)
SELA(1,0)
SELB(1,0)
SELC(1,0)
SCLK
SDATA
VDDQA
VDDQB
VDDQC
AVDD
VDD
AVSS
VSS
[1]
Name
Supply
Supply
Supply
Supply
Supply
Supply
Supply
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I/O
O
O
O
O
O
O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
Ground
Analog
Analog
Type
VDD
VDD
VDD
VDD
VDD
Crystal oscillator input.
Crystal oscillator output.
LVCMOS/LVTTL reference clock input.
LVCMOS/LVTTL reference clock input.
Clock output bank A.
Clock output bank B.
Clock output bank C.
Feedback clock output. Connect to FB_IN for normal operation.
Feedback clock input. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference clock.
See Table 1.
Synchronous pulse output. This output is used for system synchro-
nization.
PLL enable/bypass input. When Low, PLL is disabled/bypassed.
and the input clock connects to the output dividers.
Master reset and Output enable/disable input. See Table 2.
LVCMOS Clock reference select input. See Table 2.
LVCMOS/LVPECL Reference select input. See Table 2.
VCO Operating frequency select input. See Table 2.
QC(2,3) Phase selection input. See Table 2.
Feedback divider select input. See Table 6.
Frequency select input, Bank A. See Table 3.
Frequency select input, Bank B. See Table 4.
Frequency select input, Bank C. See Table 5.
Serial Clock input.
Serial Data input.
2.5V or 3.3V Power supply for bank A output clocks.
2.5V or 3.3V Power supply for bank B output clocks.
2.5V or 3.3V Power supply for bank C output clocks.
2.5V or 3.3V Power supply for PLL.
2.5V or 3.3V Power supply for core and inputs.
Analog Ground.
Common Ground.
Description
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CY29772
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