cy29962 Cypress Semiconductor Corporation., cy29962 Datasheet

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cy29962

Manufacturer Part Number
cy29962
Description
2.5v/3.3v, 150-mhz Multi-output Zero Delay Buffer Semiconductor
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number:
cy29962AI
Quantity:
25
Cypress Semiconductor Corporation
Document #: 38-07364 Rev. *B
Features
Table 1. Frequency Table
Note:
• 2.5V or 3.3V operation
• Output frequency up to 150MHz
• Supports PowerPC
• 21 clock outputs: drive up to 42 clock lines
• LVPECL or LVCMOS/LVTTL clock input
• Output-to-output skew < 150 ps
1.
Block Diagram
SELA
PECL_CLK#
Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1) or 25 MHz to 50 MHz (FB_SEL = 0).
PECL_CLK
0
1
REF_SEL
FB_SEL
FB_IN
SELC
TCLK
SELA
SELB
OE#
VCO/2
VCO/4
QA
0
1
®
PLL
REF
FB
2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer
and Pentium
[1]
AVDD
0
1
SELB
/12
/2
/4
/8
0
1
®
processors
0
1
0
1
0
1
0
1
D Q
D Q
D Q
D Q
3901 North First Street
A
B
C
FB
VCO/2
VCO/4
QB
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FB_OUT
SELC
• Split 2.5V/3.3V outputs
• Spread-spectrum-compatible
• Glitch-free output clocks transitioning
• Output disable control
• Pin-compatible with MPC9600
• Industrial temperature range: –40°C to +85°C
• 48-pin TQFP package
PEC L_C LK#
0
1
PEC L_C LK
R EF_SEL
Pin Configuration
F B_SEL
AVD D
VSSC
SELC
T C LK
SELA
SELB
VD D
VSS
San Jose
VCO/2
VCO/4
1
2
3
4
5
6
7
8
9
10
11
12
QC
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
C Y 29962
CA 95134
FB_SEL
Revised December 26, 2002
0
1
CY29962
36
35
34
33
32
31
30
29
28
27
26
25
408-943-2600
FB_OUT
VCO/12
VCO/8
VSSA
FB_O U T
Q B0
Q B1
VD D B
Q B2
Q B3
VSSB
Q B4
Q B5
Q B6
VD D B

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cy29962 Summary of contents

Page 1

... VSSC FB_OUT • 3901 North First Street • San Jose CY29962 QC FB_SEL FB_OUT VCO/2 0 VCO/8 VCO/4 1 VCO/ VSSA 1 36 FB_O ...

Page 2

... Power supply for core Power Supply for PLL. When AVDD is set LOW, PLL is bypassed. Common ground for Bank A Common ground for Bank B Common ground for Bank C Common ground 0 CY29962 Description 1 PECL_CLK PLL power Outputs Disabled (except FB_OUT) Output Bank A at VCO/4 ...

Page 3

... Document #: 38-07364 Rev. *B Zero Delay Buffer When used as a zero delay buffer, the CY29962 will likely nested clock tree application. For these applications the CY29962 offers a low-voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance ...

Page 4

... Typ. Max 1.7 500 1000 V – 1 –120 1 Min. Typ. Max. V 0.8 SS 2.0 V 500 1000 V – 1 –120 120 0.55 2 CY29962 Unit 0 – 0.6 V µA 120 µA 0 Unit – 0.6 V µA µ Page ...

Page 5

... FB_SEL = 1 FB_SEL = 0 [9,10] 0.55V to 2.0V, V 0.5V to 1.8V (÷2) Q (÷4) [9] [9] [9,10] [9,10] Same Frequency Different Frequency Banks at different voltages TCLK or PECL_CLK VDD = 3.3V to FB_IN VDD = 2.5V /2 Package Type 48-pin TQFP 48-pin TQFP - Tape and Reel CY29962 [8] Min. Typ. Max 200 400 10 = 3.3V DD 0.1 1.0 =2.5V DD 100 150 ...

Page 6

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29962 51-85166-** ...

Page 7

... Document Title: CY29962 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer Document Number: 38-07364 Issue REV. ECN NO. Date ** 112490 03/06/02 *A 116092 09/03/02 *B 122906 12/26/02 Document #: 38-07364 Rev. *B Orig. of Change CTK New Data Sheet HWT Changed the Package Drawing and Dimension to CY standard on page 6. RBI Add power up requirements to maximum ratings requirements ...

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