cy29962 Cypress Semiconductor Corporation., cy29962 Datasheet
cy29962
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cy29962 Summary of contents
Page 1
... VSSC FB_OUT • 3901 North First Street • San Jose CY29962 QC FB_SEL FB_OUT VCO/2 0 VCO/8 VCO/4 1 VCO/ VSSA 1 36 FB_O ...
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... Power supply for core Power Supply for PLL. When AVDD is set LOW, PLL is bypassed. Common ground for Bank A Common ground for Bank B Common ground for Bank C Common ground 0 CY29962 Description 1 PECL_CLK PLL power Outputs Disabled (except FB_OUT) Output Bank A at VCO/4 ...
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... Document #: 38-07364 Rev. *B Zero Delay Buffer When used as a zero delay buffer, the CY29962 will likely nested clock tree application. For these applications the CY29962 offers a low-voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance ...
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... Typ. Max 1.7 500 1000 V – 1 –120 1 Min. Typ. Max. V 0.8 SS 2.0 V 500 1000 V – 1 –120 120 0.55 2 CY29962 Unit 0 – 0.6 V µA 120 µA 0 Unit – 0.6 V µA µ Page ...
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... FB_SEL = 1 FB_SEL = 0 [9,10] 0.55V to 2.0V, V 0.5V to 1.8V (÷2) Q (÷4) [9] [9] [9,10] [9,10] Same Frequency Different Frequency Banks at different voltages TCLK or PECL_CLK VDD = 3.3V to FB_IN VDD = 2.5V /2 Package Type 48-pin TQFP 48-pin TQFP - Tape and Reel CY29962 [8] Min. Typ. Max 200 400 10 = 3.3V DD 0.1 1.0 =2.5V DD 100 150 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29962 51-85166-** ...
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... Document Title: CY29962 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer Document Number: 38-07364 Issue REV. ECN NO. Date ** 112490 03/06/02 *A 116092 09/03/02 *B 122906 12/26/02 Document #: 38-07364 Rev. *B Orig. of Change CTK New Data Sheet HWT Changed the Package Drawing and Dimension to CY standard on page 6. RBI Add power up requirements to maximum ratings requirements ...