cy25c01 Cypress Semiconductor Corporation., cy25c01 Datasheet - Page 5

• Manufacturer Part Number: cy25c01
• Description: 1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, And 16 Kbit X8 Spi Serial Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Table 3. Status Register Format for CY25C01/02/04
Table 4. Status Register Format for CY25C08/16
Table 5. Status Register Bit Definition
Write Status Register (WRSR)
The WRSR instruction enables the user to select one of four
levels of protection. The CY25C01/02/04/08/16 is divided into
four array segments. One quarter, one half, or all of the memory
segments can be protected. Any of the data within any selected
segment is therefore read only. The block write protection levels
and corresponding status register control bits are shown in
Table
The three bits BP0, BP1, and WPEN
have the same properties and functions as the regular memory
cells (for example, WREN, t
Table 6. Block Write Protect Bits
Table 7. WPEN Operation
Document #: 001-15633 Rev. *C
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4–6 are ‘0’s when device is not in an internal write cycle.
Bit 7 (X / WPEN) When the device is not in an internal write cycle, this bit is 0 in CY25C01/02/04 and WPEN (See
Bits 0–7 are ‘1’s during an internal write cycle.
WPEN
WPEN
Bit 7
Bit 7
1 (1/4)
2 (1/2)
6.
Level
3 (All)
X
Bit
X
X
0
0
1
1
0
Bit 0 = ‘0’ (RDY) indicates the device is READY. Bit 0 = ‘1’ indicates the write cycle is in progress.
Bit 1= ‘0’ indicates the device is not WRITE ENABLED. Bit 1 = ‘1’ indicates the device is write enabled.
See
See
Table 7
Bit 6
Bit 6
Table
Table
High
High
Low
Low
X
X
WP
X
X
on page 5) in CY25C08/16
BP1
WC
0
0
1
1
6.
6.
Status Register Bits
, RDSR).
[1]
WEN
Bit 5
Bit 5
are nonvolatile cells that
0
X
X
0
1
1
0
1
BP0
Protected Blocks
0
1
0
1
Bit 4
Bit 4
Protected
Protected
Protected
Protected
Protected
Protected
X
X
CY25C01
60 - 7F
40 - 7F
00 - 7F
None
The WRSR instruction in CY25C08/16 also allows the user to
enable or disable the write protect (WP) pin using the Write
Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is ‘1’. Hardware write
protection is disabled when the WP pin is high or when the
WPEN bit is ‘0’ (See
When the device is hardware write protected, writes to the status
register, including the block protect bits and the WPEN
the block protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory that are not
block protected.
Definition
Bit 3
Bit 3
BP1
BP1
Unprotected Blocks
CY25C02
C0 - FF
80 - FF
00 - FF
None
Array Addresses Protected
Protected
Protected
Protected
Writable
Writable
Writable
Bit 2
Bit 2
BP0
BP0
Table
CY25C04
180 - 1FF
100 - 1FF
000 - 1FF
None
7).
CY25C01/02/04/08/16
WEN
WEN
Bit 1
Bit 1
0300 - 03FF 0600 - 07FF
0200 - 03FF 0400 - 07FF
0000 - 03FF 0000 - 07FF
CY25C08
None
Status Register
Protected
Protected
Protected
Protected
Writable
Writable
Page 5 of 17
CY25C16
Bit 0
RDY
Bit 0
RDY
[1]
None
bit, and
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