cy23fs04 Cypress Semiconductor Corporation., cy23fs04 Datasheet
cy23fs04
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cy23fs04 Summary of contents
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... DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS04 is that the DCXO is in fact the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchro- nizes to the external clock ...
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... PLL, greatly simplifying system design. The CY23FS04 PLL is driven by the crystal oscillator, which is phase-aligned to an external reference clock so that the output of the device is effectively phase-aligned to reference via the external feedback loop. This is accomplished by utilizing a ...
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... DCXO maintains its last setting and a flag signal (FAIL#/SAFE) is set to indicate failure of the reference clock. The CY23FS04 provides 2 select bits, S1 through S2 to control the reference to crystal frequency ratio. The DCXO is internally tuned to the phase and frequency of the external reference ...
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... Failsafe typical frequency settling time Initial valid Ref1=20MHz +100ppm, 150 100 Figure 4. FailSafe Reference Switching Behavior Figure 5. FailSafe Effective Loop Bandwidth (min) Document #: 38-07304 Rev. *C then switching to REF2=20MHz 0.45 1.3 SETTLING TIME (ms) CY23FS04 2.5 Page [+] Feedback ...
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... Figure 6. Sample Timing of Muxing Between Two Reference Clocks 180°C Out of Phase and Resulting Output Phase Offset Typical Settling Time (105 MHz) 190 fs/ Figure 7. Resulting Output dphase/Cycle Typical Rate of Change (105 MHz) Document #: 38-07304 Rev 190 fsec/cycle = 0.125 mradian/cycle CY23FS04 1.4 ms Page [+] Feedback ...
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... S ta tic ffs (φ ) Document #: 38-07304 Rev (φ CY23FS04 Page [+] Feedback ...
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... Plotting the pullability of the XTAL shows this expected behavior as shown in Figure 8. In this example, specifying a XTAL calibrated load provides a balanced ppm pullability range around the nominal frequency. = ((C1)/2)[(1/(C0+Clmin))–(1/(C0+Clmax))] × 10 CY23FS04 6 Page [+] Feedback ...
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... Positive Capture Range = 333 ppm – 53 ppm = +280 ppm It is important to note that the XTAL with lower C0/C1 ratio has wider pullability/capture range as compared to the higher C0/C1 ratio. This will help the user in selecting the appropriate XTAL for use in the FailSafe application. CY23FS04 C0/C1 = 200 C0/C1 = 300 C0/C1 = 400 Page ...
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... Comments Parallel resonance, fundamental mode, AT cut Fundamental mode Ratio used because typical R values 1 are much less than the maximum spec No external series resistor assumed High side NOM Low side NOM Description CY23FS04 Min. Max. Unit –0.5 4.6 V –0.5 V +0.5 VDC DD –65 +150 °C ...
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... Ordering Information Part Number CY23FS04ZI CY23FS04ZIT CY23FS04ZC CY23FS04ZCT Lead-free CY23FS04ZXI CY23FS04ZXIT CY23FS04ZXC CY23FS04ZXCT Notes The reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as ( φ Parameters guaranteed by design and characterization, not 100% tested in production. ...
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... DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 6.25[0.246] PACKAGE WEIGHT 0.05 gms 6.50[0.256] Z16.173 ZZ16.173 LEAD FREE PKG. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY23FS04 MAX. PART # STANDARD PKG. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85091-*A Page [+] Feedback ...
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... Document History Page Document Title: CY23FS04 Failsafe™ 2.5V/ 3.3V Zero Delay Buffer Document #: 38-07304 Rev. *C Orig. of REV. ECN NO. Issue Date Change ** 123698 04/24/03 *A 223811 See ECN RGL/ZJX Changed the XTAL Specifications table. *B 276712 See ECN *C 378918 See ECN Document #: 38-07304 Rev. *C Description of Change ...