cy23fs04 Cypress Semiconductor Corporation., cy23fs04 Datasheet - Page 2

• Manufacturer Part Number: cy23fs04
• Description: 2.5v/ 3.3v Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07304 Rev. *C
Pin Definition
Table 1. Configuration Table
FailSafe Function
The CY23FS04 is targeted at clock distribution applications
that could or which currently require continued operation
should the main reference clock fail. Existing approaches to
this requirement have utilized multiple reference clocks with
either internal or external methods for switching between
references. The problem with this technique is that it leads to
interruptions (or glitches) when transitioning from one
reference to another, often requiring complex external circuitry
or software to maintain system stability. The technique imple-
Notes:
1,2
3,4
14,13
15
12,5
8
9
10
11
7
6
16
1. For normal operation, connect either one of the four clock outputs to the FBK input.
2. Weak pull-downs on all outputs
3. Weak pull-ups on these inputs.
4. Weak pull-down on these inputs.
S[2:1]
F a i l # / S a f e
O U T
Pin Number
R E F
00
01
10
11
Min.
8.33
8.00
8.33
XTAL (MHz)
REF[1:2]
CLKB[1:2]
CLKA[1:2]
FBK
S[1:2]
XIN
XOUT
FAIL#/SAFE
VDD
VDDC
VSS
REFSEL
Pin Name
30.00
25.00
28.33
Max.
Figure 1. Fail#/Safe Timing for Input Reference Failing Catastrophically
16.00
50.00
t
Min.
4.17
Reference clock inputs. 5V-tolerant
Bank B clock outputs.
Bank A clock outputs.
Feedback input to the PLL.
Frequency select pins and PLL and DCXO bypass mode.
Reference crystal input.
Reference crystal output.
Valid reference indicator. A high level indicates a valid reference input.
2.5V or 3.3V power supply.
3.3V power supply.
Ground.
Reference select. Selects the active reference clock from either REF1 or REF2. REFSEL
= 1, REF1 is selected, REFSEL = 0, REF2 is selected.
F S L
REF (MHz)
170.00
15.00
50.00
Max.
16.00
50.00
Min.
4.17
[1,2]
[1,2]
OUT (MHz)
PLL and DCXO Bypass Mode
[1,4]
mented in this design completely eliminates any switching of
references to the PLL, greatly simplifying system design.
The CY23FS04 PLL is driven by the crystal oscillator, which is
phase-aligned to an external reference clock so that the output
of the device is effectively phase-aligned to reference via the
external feedback loop. This is accomplished by utilizing a
digitally controlled capacitor array to pull the crystal frequency
over an approximate range of +300 ppm from its nominal
frequency.
170.00
15.00
50.00
Max.
[4]
Description
.
REF:OUT ratio
x1
x1
x1
t
F S H
[3]
REF:XTAL
ratio
1/2
2
6
CY23FS04
Out:XTAL
Page 2 of 12
ratio
1/2
2
6
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