cy28rs600-2 SpectraLinear Inc, cy28rs600-2 Datasheet - Page 11

• Manufacturer Part Number: cy28rs600-2
• Description: Clock Generator For Ati Rs5xx, 6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 3 is an example showing the relationship of
clocks coming up.
RESET_IN# Assertion
The RESET_IN# is a negative edge triggered signal. When
asserted, all PLLs will revert back to a safe default frequency.
CPUC, 133MHz
CPUT, 133MHz
CPUC, 133MHz
CPUT, 133MHz
ATIGC 100MHz
SRCC 100MHz
ATIGT 100MHz
SRCT 100MHz
ATIGC/SRCC
ATIGT/SRCT
PCI, 33 MHz
Figure 4. RESET_IN# Assertion/Deassertion Waveform
USB, 48MHz
PCI, 33MHz
USB, 48MHz
100MHz
100MHz
Figure 3. PWRDWN Assertion/Deassertion Waveform
REF
REF
PD
INFORMATION
ADVANCE
<300μS, >200mV
Tstable
<1.8ms
Tdrive_PD
The clock output will be allowed to turn off for a maximum of
4 ms. After this time the PLLs will output a locked clock at a
preselected safe frequency. The safe frequency is either
based upon the power on reset default values or upon the
value stored in the safe frequency register. The safe frequency
register is accessible via SMBUS (Bytes 18 & 19). The clock
outputs must be stable at the correct safe frequency at least
2 ms before the deassertion of RESET_IN#.
CY28RS600-2
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