cy22313 Cypress Semiconductor Corporation., cy22313 Datasheet
cy22313
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cy22313 Summary of contents
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... S 0 VDDR 1 53.94605395 VSSR CLK S CLK, CLKB CLKB 0 VSSR 1 VDDR NC VDDL VSSL LCLK VSSVP • 3901 North First Street • San Jose CY22313 ® output LCLK 54MOUT CLK CLKB 54MOUT Unit PPM 54 MHz 0 MHz –1 Unit PPM 294.912 MHz 0 393.216 MHz 0 ...
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... Power for LCLK Do Not Connect, Leave Floating Power for DRCG CLK/CLKB Ground for DRCG CLK/CLKB Output Clock to Rambus (complement) Output Clock to Rambus Ground for DRCG CLK/CLKB Power for DRCG CLK/CLKB Frequency Select Pin for DRCG CLK/CLKB (internal pull-up resistor) CY22313 Page [+] Feedback ...
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... Except crystal pins CMOS levels DDRP DDVPA CMOS levels DDRP DDVPA Pull-down resistor on FS Pull-up resistor on S Sum of all supply currents [3] Description [5] [6] [ board layout as implemented with the original crystal-driven IN OUT CY22313 + 0.5V) DD Min. Typ Max. Unit 3.15 3.45 3.6 V 2.25 2.5 2.75 V 1.6 1.675 1.75 V 1.6 1.8 2.0 V ...
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... Cycle-Cycle Jitter, 1–6 Cycles, 400 MHz Cycle-Cycle Jitter, 1–6 Cycles, 300 MHz [15] Long-term Jitter, 400 MHz Long-term Jitter, 300 MHz [16] Cycle-Cycle Duty Cycle Error, 400 MHz Cycle-Cycle Duty Cycle Error, 300 MHz CY22313 Min. Typ. Max. Unit [8] ±5 ±10 PPM [9] ± ...
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... Document #: 38-07434 Rev Output stable within PPM spec. 5 Figure 2. PLL Lock Time t t cycle,i+1 cycle cycle,i - cycle,i+1 1000 cycles ... ... t t 1000cycle,i+1 1000cycle 1000cycle,i - 1000cycle,i+1 Figure 4. 54MOUT, LCLK 1000 Cycle Jitter CY22313 Vx Page [+] Feedback ...
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... CYLCE,i CYCLE,i+1 Figure 5. CLK, CLKB Cycle-to-Cycle Jitter - t 4CYCLE,i+1 over 10000 consecutive cycles = t – t over 10000 cycles 9 CYCLE,max CYCLE,min Figure 7. CLK, CLKB Long-term Jitter Cycle i+1 t PW+,i t CYCLE,i – PW+,i PW+,i+1 Figure 8. CLK, CLKB Duty Cycle Error CY22313 t 4CYCLE,i+1 t PW+,i+1 Page [+] Feedback ...
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... Measurement Point Figure 9. Direct Rambus Test Circuit OUTPUTS GND Value 68 39 [17] 15 0.01 Package Type Operating Range Commercial (T Commercial (T Commercial (T Commercial (T CY22313 = MID = Z CH CLK out C LOAD Tolerance Unit Ω ±5% Ω ±5% ±10% pF µF ±20% Operating Voltages = 0°C to 85°C) 3 ...
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... Cypress against all charges. PIN 6.25[0.246] 6.50[0.256] DIMENSION IN MM(INCHES) 4.30[0.169] 4.50[0.177] 24 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] 0.05[0.002] SEATING 0.15[0.006] PLANE CY22313 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85119-*A Page [+] Feedback ...
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... Document History Page Document Title: CY22313 Two-PLL Clock Generator with Direct Rambus™ (Lite) Support Document Number: 38-07434 Issue Orig. of REV. ECN NO. Date Change ** 117092 07/02/02 CKN *A 121365 11/15/02 CKN *B 121773 02/17/03 CKN *C 125454 05/19/03 CKN *D 127393 06/12/03 RGL *E 239051 See ECN RGL Document #: 38-07434 Rev. *E ...