ds7800h National Semiconductor Corporation, ds7800h Datasheet - Page 3

• Manufacturer Part Number: ds7800h
• Description: Dual Voltage Level Translator
• Manufacturer: National Semiconductor Corporation

Theory of Operation
The two input diodes perform the AND function on TTL in-
put voltage levels When at least one input voltage is a logi-
cal ‘‘0’’ current from V
R
than small leakage currents this current drawn from V
through the 20 kX resistor is the only source of power dissi-
pation in the logical ‘‘1’’ output state
When both inputs are at logical ‘‘1’’ levels current passes
through R
thus pulling current through R
the PNP transistor Q
rent through Q
voltage sufficient to overcome these losses before current
begins to flow To achieve this voltage at node P the inputs
must be raised to a voltage level which is one diode poten-
tial lower than node P Since these levels are exactly the
same as those experienced with conventional TTL the in-
terfacing with these types of circuits is achieved
Transistor Q
output due to the common base connection of Q
least one input is at the logical ‘‘0’’ level no current is deliv-
ered to Q
current to the output stage But when both inputs are raised
to a logical ‘‘1’’ level current is supplied to Q
Selecting Power Supply Voltage
The graph shows the boundary conditions which must be
used for proper operation of the unit The range of operation
for power supply V
between
supply V
V
passing through the V
ries of the operating region A voltage difference between
power supplies of at least 5V should be maintained for ade-
quate signal swing
Switching Time Waveforms
2
1
and out the input(s) which is at the low voltage Other
V
3
may be selected as any value along a vertical line
3
b
is governed by supply V
1
2
25V and
and diverts to transistor Q
2
so that its collector supplies essentially zero
1
provides ‘‘constant current switching’’ to the
D
3
2
and Q
b
2
2
is shown on the X axis It must be
CC
value and terminated by the bounda-
8V The allowable range for power
The voltage losses caused by cur-
2
(nominally 5 0V) passes through
necessitate that node P reach a
2
Current is then supplied to
2
With a value chosen for
1
turning it on and
2
2
When at
CC
3
Since this current is relatively constant the collector of Q
acts as a constant current source for the output stage Logic
inversion is performed since logical ‘‘1’’ input voltages
cause current to be supplied to Q
turns on the output voltage drops to the logical ‘‘0’’ level
The reason for the PNP current source Q
output stage can be driven from a high impedance This
allows voltage V
application Negative voltages to
V
amounts of current the output voltage range is almost ex-
clusively dependent upon the values selected for V
Maximum leakage current through the output transistor Q
is specified at 10 mA under worst-case voltage between V
and V
is 0 2V below V
D
falling lower than 2V above V
voltage swing at typically 2 volts less than the voltage sepa-
ration between V
2
5
and D
Since the output will neither source nor sink large
3
This will result in a logical ‘‘1’’ output voltage which
6
prevents the logical ‘‘0’’ output voltage from
3
2
2
Likewise the clamping action of diodes D
and V
to be adjusted in accordance with the
3
2
thus establishing the ouput
b
2
25V can be applied to
and Q
TL F 5827 – 6
3
2
And when Q
is so that the
TL F 5827 – 5
2
and V
3
4
3
2
2
3