ds2764aet-r Maxim Integrated Products, Inc., ds2764aet-r Datasheet - Page 18

• Manufacturer Part Number: ds2764aet-r
• Description: Ds2764 High-precision Li+ Battery Monitor With 2-wire Interface
• Manufacturer: Maxim Integrated Products, Inc.

Bus Timing
The DS2764 is compatible with any bus timing up to 100kHz. No special configuration is required to operate at any
speed.
2-Wire Command Protocols
The command protocols involve several transaction formats. The simplest format consists of the master writing the
START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the DS2764. More
complex formats such as the Write Data, Read Data and Function command protocols write data, read data and
execute device specific operations. All bytes in each command format require the slave or host to return an
Acknowledge bit before continuing with the next byte. Each function command definition outlines the required
transaction format. The following key applies to the transaction formats.
Table 3. 2-Wire Protocol Key
Basic Transaction Formats
Write:
A write transaction transfers one or more data bytes to the DS2764. The data transfer begins at the memory
address supplied in the MAddr byte.
transaction, except for the Acknowledge cycles.
Read:
A read transaction transfers one or more bytes from the DS2764. Read transactions are composed of two parts, a
write portion followed by a read portion, and is therefore inherently longer than a write transaction. The write
portion communicates the starting point for the read operation. The read portion follows immediately, beginning
with a Repeated START, Slave Address with R/W set to a 1. Control of SDA is assumed by the DS2764 beginning
with the Slave Address Acknowledge cycle. Control of the SDA signal is retained by the DS2764 throughout the
transaction, except for the Acknowledge cycles. The master indicates the end of a read transaction by responding
to the last byte it requires with a No Acknowledge. This signals the DS2764 that control of SDA is to remain with
the master following the Acknowledge clock.
Write Data Protocol
The write data protocol is used to write to register and shadow RAM data to the DS2764 starting at memory
address MAddr. Data0 represents the data written to MAddr, Data1 represents the data written to MAddr + 1 and
DataN represents the last data byte, written to MAddr + N. The master indicates the end of a write transaction by
sending a STOP or Repeated START after receiving the last acknowledge bit.
The msb of the data to be stored at address MAddr can be written immediately after the MAddr byte is
acknowledged. Because the address is automatically incremented after the least significant bit (lsb) of each byte is
received by the DS2764, the msb of the data at address MAddr + 1 is can be written immediately after the
acknowledgement of the data at address MAddr.
transaction beyond address 4Fh, the DS2764 ignores the data. Data is also ignored on writes to read-only
addresses and reserved addresses, locked EEPROM blocks as well as a write that auto increments to the Function
Command register (address FEh). Incomplete bytes and bytes that are Not Acknowledged by the DS2764 are not
written to memory. As noted in the Memory Section, writes to unlocked EEPROM blocks modify the shadow RAM
only.
S
SAddr
FCmd
MAddr
Data
A
N
KEY
S SAddr W A MAddr A Data0 A Data1 A … DataN A P
S SAddr W A MAddr A Data0 A P
S SAddr W A MAddr A Sr SAddr R A Data0 N P
Slave Address (7-bit)
Function Command byte
Memory Address byte
Data byte written by master
No Acknowledge - Master
START bit
Acknowledge bit - Master
Write Portion
DESCRIPTION
Control of the SDA signal is retained by the master throughout the
Read Portion
Data
KEY
18 of 20
Sr
W
R
P
A
N
If the bus master continues an auto-incremented write
Repeated START
R/W bit = 0
R/W bit = 1
STOP bit
Data byte returned by slave
Acknowledge bit¾Slave
No Acknowledge¾Slave
DESCRIPTION