ds2764aet-r Maxim Integrated Products, Inc., ds2764aet-r Datasheet - Page 9

• Manufacturer Part Number: ds2764aet-r
• Description: Ds2764 High-precision Li+ Battery Monitor With 2-wire Interface
• Manufacturer: Maxim Integrated Products, Inc.

POWER MODES
The DS2764 has two power modes: active and sleep. While in active mode, the DS2764 continually measures
current, voltage, and temperature to provide data to the host system and to support current accumulation and Li+
safety monitoring. In sleep mode, the DS2764 ceases these activities. The DS2764 enters sleep mode when any of
the following conditions occurs:
§
§
The DS2764 returns to active mode when any of the following occurs:
§
§
§
The DS2764 defaults to active mode when power is first applied.
Li+ PROTECTION CIRCUITRY
During active mode, the DS2764 constantly monitors cell voltage and current to protect the battery from overcharge
(overvoltage), overdischarge (undervoltage), and excessive charge and discharge currents (overcurrent, short
circuit). Conditions and DS2764 responses are described in the following sections and summarized in Table 1 and
Figure 4.
Table 1. Li+ Protection Conditions and DS2764 Responses
V
Overvoltage. If the cell voltage on V
delay, t
cell voltage falls below charge enable threshold V
protection condition prevents it). Discharging remains enabled during overvoltage, and the DS2764 re-enables the
charge FET before V
Undervoltage. If the voltage of the cell drops below undervoltage threshold, V
undervoltage delay, t
register, and enters sleep mode. The DS2764 provides a recovery charge path from PLS to V
DS2764 by the charger when the cell is severely depleted. Once the DS2764 regains power it will enter active
mode of operation and allow full charging of the cell. The recovery charge path is disabled when the cell voltage is
above 3.0V to prevent cell overcharge through the PLS pin.
Overcurrent, Discharge
Short Circuit
Overvoltage
Undervoltage
Overcurrent, Charge
IS
Note 1:
Note 2:
Note 3:
Note 4:
= V
The PMOD bit in the Status Register has been set to 1 and both SCL and SDA are low for longer
than 2.1s (pack disconnection).
The voltage on V
The PMOD bit has been set to 1 and either the SDA or SCL line is pulled high (pack connection).
The PS pin is pulled low (power switch).
The voltage on PLS becomes greater than the voltage on V
IS1
CONDITION
OVD
- V
IS2
, the DS2764 shuts off the external charge FET and sets the OV flag in the protection register. When the
If V
exceed 2.2V.
For the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of current: I
direction and I
With test current I
With test current I
. Logic high = V
DD
< 2.2V, release is delayed until the recovery charge current passed from PLS to V
IN
IN
UVD
SNS
< V
drops below undervoltage threshold V
PLS
, the DS2764 shuts off the charge and discharge FETs, sets the UV flag in the protection
TST
TST
< -I
CE
for CC and V
flowing from PLS to V
flowing from V
THRESHOLD
OC
if a discharge current of -80mA (V
V
V
V
V
V
IS
for discharge direction.
IS
SNS
IN
IN
< -V
> V
> V
< V
> V
OC
OC
IN
OV
UV
DD
SC
(2)
(2)
exceeds the overvoltage threshold, V
for DC
DD
to PLS (pullup on PLS).
.
All voltages are with respect to V
SS
(pulldown on PLS).
ACTIVATION
DELAY
CE
t
t
t
t
t
OVD
UVD
OCD
OCD
SCD
, the DS2764 turns the charge FET back on (unless another
9 of 20
UV
IS
DD
for t
≤ -2mV) or less is detected.
(charger connection).
UVD
CC, DC high,
RESPONSE
CC, DC high
Sleep Mode
CC high
DC high
DC high
(cell depletion).
SS
. I
SNS
OV
references current delivered from pin SNS.
, for a period longer than overvoltage
DD
charges the battery and allows V
UV
, for a period longer than
RELEASE THRESHOLD
(charger connected)
V
V
V
PLS
PLS
PLS
V
V
V
PLS
IN
SNS
< V
> V
> V
IS
< V
≤ -2mV
DD
> V
DD
DD
DD
> I
CE
to power the
OC
DD
- V
- V
- V
, or
(1)
for charge
TP
TP
TP
(3)
(4)
(4)
DD
to