ds1075 ETC-unknow, ds1075 Datasheet - Page 6

• Manufacturer Part Number: ds1075
• Description: Econoscillator/divider
• Manufacturer: ETC-unknow

Disable Timing
If OE goes low while OUT is high, the output will be dis-
abled on the completion of the output pulse. If OUT is
low, the disabling behavior will be dependent on the
setup time between the falling edge of OE and the rising
edge of MCLK. If t
tional pulse appearing on the output before disabling
occurs.
Figure 5
Figure 6
SELECT TIMING
If the PDN bit is set to “0”, the PDN/SELX pin can be
used to switch between the internal oscillator and an
external or crystal reference. The “Enabling Sequencer”
is again employed to ensure this transition occurs in a
glitch–free fashion. Two asynchronous clock signals
are involved, INTCLK is the internal reference oscillator
DS1075
101697 6/16
MCLK
MCLK
OUT
OUT
OE
OE
N = 1
N
2
SU
t
t
SU
SU
< t
SUEM
t
d
t
the result will be one addi-
d
t
t
M
M
t
dis
t
t
dis
OUTH
t
OUTH
If the device is in divide–by–one mode, the disabling
occurs slightly differently. In this case if t
additional output pulse will appear, if t
two additional output pulses will appear.
The following diagrams illustrate the timing in each of
these cases.
divided by one or whatever value of M is selected.
EXTCLK is the clock signal fed into the OSCIN pin, or
the clock resulting from a crystal connected between
OSCIN and XTAL. The behavior of OUT0 is described in
the following paragraphs, the OUT pin will behavior sim-
ilarly but will be divided by N.
t
t
t
MAX VALUE OF t
MIN VALUE OF t
t
t
t
MAX VALUE OF t
MIN VALUE OF t
M
d
OUTH
M
d
OUTH
= PROP DELAY FROM MCLK
= PERIOD OF MCLK
= PROP DELAY FROM MCLK
= PERIOD OF MCLK
= WIDTH OF OUTPUT PULSE
= WIDTH OF OUTPUT PULSE
dis
dis
dis
dis
= t
= 0
= t
= t
SUEM
SUEM
SUEM
+ t
+ t
SU
+ t
SU
d
d
d
+ t
< t
+ t
+ t
TO OUT
> t
TO OUT
OUTH
OUTH
OUTH
SUEM
SUEM
+ t
M
then
one