ds1075 ETC-unknow, ds1075 Datasheet - Page 7

• Manufacturer Part Number: ds1075
• Description: Econoscillator/divider
• Manufacturer: ETC-unknow

From Internal to External clock
This is accomplished by a high to low transition on the
SELX pin. This transition is detected on the falling edge
of INTCLK. The output OUT0 will be held low for a mini-
Figure 7
Depending on the relative timing of the SELX signal and
the internal clock, there may be up to one full cycle of t
on the output after the falling edge of SELX. Then, the
“low” time (t
dent on the relative timing between t
interval between the falling edge of SELX and the first
rising edge of the externally derived clock is t
Approximate maximum and minimum values of these
parameters are:
NOTE:
In each case there will be a small additional delay due to
internal propagation delays.
Figure 8
Depending on the relative timing of the SELX signal and
the external clock, there may be up to one full t
period on the output after the rising edge of SELX. Then,
the “low” time (t
dependent on the relative timing between t
OUT0
SELX
OUT0
SELX
t
t
t
t
LOW
LOW
SIE
SIE
(min) = t
(max) = 3t
LOW
(min) = t
(max) = t
t
Elow
) between output pulses will be depen-
LOW
I
/2
I
/2
) between output pulses will be
I
I
/2 + t
/2 + t
t
E
t
E
E
Ehigh
t
I
I
and t
t
SEI
I
E
and t
. The time
t
LOW
t
SIE
E
. The
Ehigh
SIE
I
.
t
LOW
mum of half the period of INTCLK (t
is low it will be routed through to OUT0. If EXTCLK is
high the switching will not occur until EXTCLK returns to
a low level.
From External to Internal clock
This is accomplished by a low to high transition on the
SELX pin. In this case the switch is level triggered, to
allow for the possibility of a clock signal not being pres-
ent at OSCIN. Note therefore, that if a constant high–
level signal is applied to OSCIN it will not be possible to
switch over to the internal reference. (Level triggering
was not employed for the switch from internal to external
reference as this approach is slower and the internal
clock may be running at a much higher frequency than
the maximum allowed external clock rate). When SELX
is high and a low level is sensed on EXTCLK, OUT0 will
be held low until a falling edge occurs on INTCLK, then
the next rising edge of INTCLK will be routed through to
OUT0.
time interval between the falling edge of SELX and the
first rising edge of the externally derived clock is t
Approximate maximum and minimum values of these
parameters are:
t
I
t
t
I
E
= PERIOD OF INTERNAL CLOCK
= PERIOD OF EXTERNAL CLOCK
= t
Elow
+ t
t
t
I
E
= PERIOD OF INTERNAL CLOCK
Ehigh
= PERIOD OF EXTERNAL CLOCK
t
E
I
/2), then if EXTCLK
101697 7/16
DS1075
SIE
.