upd64a Renesas Electronics Corporation., upd64a Datasheet - Page 17

• Manufacturer Part Number: upd64a
• Description: 4-bit Single-chip Microcontroller For Infrared Remote Control Transmission
• Manufacturer: Renesas Electronics Corporation.

3.2.4 S
register is set to 1) (at this time, a pull-down resistor is connected internally). When the STOP mode release is
disabled (bit 3 of P4 register is set to 0), this port can be used as an input port that does not release the STOP
mode even if the release condition is established (at this time, a pull-down resistor is not connected internally).
state.
3.3 Control Register 0 (P3)
The S
Use of a STOP mode release for the S
When using this port as a key input from a key matrix, enable the use of the STOP mode release (bit 3 of P4
The state of the pin can be read in both cases.
After reset, the pin is set to input mode in which the STOP mode release is disabled, and enters a high-impedance
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.
After reset, the register becomes 0000 0011B.
b
b
b
b
Note Set DP
Remark
0
2
3
4
, b
:
:
, b
2
1
5
: These bits specify the carrier frequency and duty ratio of the REM output.
, b
2
port (bit 1 of P1)
This bit specifies the availability of the carrier of the frequency specified by b
This bit changes the carrier frequency and the timer clock’s frequency division ratio.
port is an input port.
Bit
Name
Set
value
After reset
6
“0” = ON (with carrier); “1” = OFF (without carrier; high level)
“0” = 1/1 (carrier frequency: The specified value of b
“1” = 1/2 (carrier frequency: Half of the specified value of b
: These bits specify the higher 3 bits (DP
: don’t care
0
1
10
b
3
of the PD64A to 0.
0
1
0
1
0
1
b
Fixed
to “0”
0
7
b
Table 3-5. Timer Clock and Carrier Frequency Settings
—
2
0
0
1
1
0
0
1
1
b
DP
0
1
0
b
6
1
10
Table 3-4. Control Register 0 (P3)
Note
DP (Data Pointer)
0
1
0
1
0
1
0
1
2
b
port can be specified by bit 3 of the P4 register.
b
DP
0
1
0
0
Data Sheet U14380EJ3V0DS00
5
9
f
f
X
X
/64
/128
Timer Clock
8
, DP
b
DP
0
1
0
4
8
9
and DP
b
1/1
1/2
0
TCTL
0
3
and b
10
Carrier Frequency (Duty Ratio)
) of ROM’s data pointer.
f
f
f
f
Without carrier (high level)
f
f
f
f
Without carrier (high level)
0
X
X
X
X
X
X
X
X
1
/8 (Duty 1/2)
/64 (Duty 1/2)
/96 (Duty 1/2)
/96 (Duty 1/3)
/16 (Duty 1/2)
/128 (Duty 1/2)
/192 (Duty 1/2)
/192 (Duty 1/3)
; timer clock: f
and b
b
ON
OFF
0
CARY
2
1
; timer clock: f
b
MOD
Refer to Table 3-5.
1
1
X
0
/64)
1
and b
X
b
MOD
1
/128)
1
0
PD64A, 65
.
0
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