74AHCT74PW,112 NXP Semiconductors, 74AHCT74PW,112 Datasheet
74AHCT74PW,112
Specifications of 74AHCT74PW,112
74AHCT74PW
935263077112
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74AHCT74PW,112 Summary of contents
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Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 05 — 9 June 2008 1. General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC74 74AHC74D +125 C 74AHC74PW +125 C 74AHC74BQ +125 C 74AHCT74 74AHCT74D +125 C 74AHCT74PW +125 C 74AHCT74BQ +125 C 4. Functional diagram Fig 1. Functional diagram 74AHC_AHCT74_5 Product data sheet 74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger ...
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... NXP Semiconductors 1SD 1CP 1RD 1 2SD 2CP 2RD 13 Fig 2. Logic symbol Fig 4. Logic diagram (one flip-flop) 74AHC_AHCT74_5 Product data sheet Dual D-type flip-flop with set and reset; positive-edge trigger mna420 Fig Rev. 05 — 9 June 2008 74AHC74; 74AHCT74 mna419 IEC logic symbol ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 1RD 1CP 3 74 1SD GND 7 Fig 5. Pin configuration SO14 and TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin 1RD 1CP 3 1SD GND 2SD 10 2CP 2RD 74AHC_AHCT74_5 Product data sheet Dual D-type flip-flop with set and reset; positive-edge trigger ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Function table Control nSD nRD nCP [ HIGH voltage level LOW voltage level; = LOW to HIGH transition state after the next LOW to HIGH CP transition; n don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter 74AHC74 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 74AHCT74 V supply voltage CC V input voltage I V output voltage O T ambient temperature ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 supply current 5 input capacitance 74AHCT74 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHC74 t propagation nCP to nQ, nQ; see pd delay nSD, nRD to nQ, nQ; see Figure maximum see Figure 7 max frequency 3.6 V ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions C power MHz dissipation capacitance 74AHCT74 4 5 propagation nCP to nQ, nQ; see pd delay nSD, nRD to nQ, nQ; see Figure maximum see Figure 7 max frequency pulse width CP HIGH or LOW ...
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... NXP Semiconductors 11. Waveforms nD input nCP input nQ output nQ output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical voltage output drop that occur with the output load Fig 7. Clock pulse width, maximum frequency, set-up times, hold times and input to output propagation delays ...
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... NXP Semiconductors nCP input nSD input nRD input nQ output nQ output Measurement points are given in V and V are typical voltage output drop that occur with the output load Fig 8. Set and reset pulse widths, recovery time and input to output propagation delays Table 8. ...
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... NXP Semiconductors For test data see Table 9. Definitions for test circuit Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z T Fig 9. Load circuitry for switching times Table 9. Test data Type Input V I 74AHC74 V CC 74AHCT74 3 ...
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... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Document ID Release date 74AHC_AHCT74_5 20080609 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74AHC_AHCT74_4 20050207 74AHC_AHCT74_3 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Revision history ...