74AHCT74PW,118 NXP Semiconductors, 74AHCT74PW,118 Datasheet - Page 10

• Manufacturer Part Number: 74AHCT74PW,118
• Description: IC DUAL D F-F POS-EDG 14TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74AHCTr
• Type: D-Typer

Specifications of 74AHCT74PW,118

• Output Type: Differential
• Package / Case: 14-TSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 140MHz
• Delay Time - Propagation: 4.8ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 8mA, 8mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: AHCT
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 3.3 ns
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 4.5 V
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 5V
• Package Type: TSSOP
• Frequency (max): 80MHz
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AHCT74PW-T; 74AHCT74PW-T; 935263077118

NXP Semiconductors
11. Waveforms
74AHC_AHCT74_5
Product data sheet
Fig 7.
Measurement points are given in
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
Clock pulse width, maximum frequency, set-up times, hold times and input to output propagation delays
OL
and V
OH
are typical voltage output drop that occur with the output load.
nCP input
nQ output
nQ output
nD input
GND
GND
V
V
V
V
OH
OH
OL
OL
V
V
Table
I
I
8.
V
M
t
PLH
Rev. 05 — 9 June 2008
t
Dual D-type flip-flop with set and reset; positive-edge trigger
su
t
V
h
M
V
V
t
W
M
M
t
PHL
1/f
max
74AHC74; 74AHCT74
t
PHL
t
su
t
h
t
mna422
PLH
© NXP B.V. 2008. All rights reserved.
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