upd78f0134hgka1-9et-a Renesas Electronics Corporation., upd78f0134hgka1-9et-a Datasheet - Page 558

• Manufacturer Part Number: upd78f0134hgka1-9et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

558
Standby
function
Reset
function
Clock
monitor
Function
OSTC:
Oscillation
stabilization
time counter
status register
OSTS:
Oscillation
stabilization
time select
register
STOP mode
setting and
operation status
Reset timing
due to
watchdog timer
overflow
RESF: Reset
control flag
register
CLM: Clock
monitor mode
register
Details of
Function
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
To set the STOP mode when the high-speed system clock is used as the CPU
clock, set OSTS before executing a STOP instruction.
Before setting OSTS, confirm with OSTC that the desired oscillation stabilization
time has elapsed
If the STOP mode is entered and then released while the internal oscillation clock
is being used as the CPU clock, set the oscillation stabilization time as follows.
The oscillation stabilization time counter counts only during the oscillation
stabilization time set by OSTS. Therefore, note that only the statuses during the
oscillation stabilization time set by OSTS are set to OSTC after STOP mode has
been released.
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
Because the interrupt request signal is used to release the standby mode, if there
is an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately released if set. Thus, the STOP mode is
reset to the HALT mode immediately after execution of the STOP instruction and
the system returns to the operating mode as soon as the wait time set using the
oscillation stabilization time select register (OSTS) has elapsed.
For an external reset, input a low level for 10 s or more to the RESET pin.
During reset input, the high-speed system clock and internal oscillation clock stop
oscillating.
When the STOP mode is released by a reset, the STOP mode contents are held
during reset input. However, the port pins become high-impedance, except for
P130, which is set to low-level output.
An LVI circuit internal reset does not reset the LVI circuit.
A watchdog timer internal reset resets the watchdog timer.
Do not read data by a 1-bit memory manipulation instruction.
Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or
the internal reset signal.
If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit
1 (CLMRF) of the reset control flag register (RESF) is set to 1.
Desired OSTC oscillation stabilization time
by OSTS
APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ3V0UD
Cautions
Oscillation stabilization time set
p. 380
p. 381
p. 381
p. 381
p. 381
p. 387
p. 391
p. 391
p. 391
p. 392
p. 393
p. 398
p. 400
p. 400
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