74LVC1G175GW,165 NXP Semiconductors, 74LVC1G175GW,165 Datasheet

IC FLIP-FLOP D POS-EDGE SC-88

74LVC1G175GW,165

Manufacturer Part Number
74LVC1G175GW,165
Description
IC FLIP-FLOP D POS-EDGE SC-88
Manufacturer
NXP Semiconductors
Series
74LVCr
Type
D-Typer
Datasheet

Specifications of 74LVC1G175GW,165

Function
Master Reset
Output Type
Non-Inverted
Number Of Elements
1
Number Of Bits Per Element
1
Frequency - Clock
200MHz
Delay Time - Propagation
2.2ns
Trigger Type
Positive Edge
Current - Output High, Low
32mA, 32mA
Voltage - Supply
1.65 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
SC-70-6, SC-88, SOT-363
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC1G175GW-R
74LVC1G175GW-R
935274948165
1. General description
2. Features and benefits
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type
flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q
output.
The master reset (MR) is an asynchronous active LOW input and operates independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 4 — 4 October 2010
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
ESD protection:
±24 mA output drive (V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C.
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

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74LVC1G175GW,165 Summary of contents

Page 1

Single D-type flip-flop with reset; positive-edge trigger Rev. 4 — 4 October 2010 1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74LVC1G175GW −40 °C to +125 °C 74LVC1G175GV −40 °C to +125 °C 74LVC1G175GM −40 °C to +125 °C 74LVC1G175GF −40 °C to +125 °C 74LVC1G175GN −40 °C to +125 °C 74LVC1G175GS 4 ...

Page 3

... NXP Semiconductors Fig 3. Logic diagram. 6. Pinning information 6.1 Pinning 74LVC1G175 GND 001aag506 Fig 4. Pin configuration SOT363 and SOT457 6.2 Pin description Table 3. Pin description Symbol Pin CP 1 GND 74LVC1G175 Product data sheet Single D-type flip-flop with reset; positive-edge trigger 74LVC1G175 GND ...

Page 4

... NXP Semiconductors 7. Functional description [1] Table 4. Function table Operating mode Input MR Reset (clear) L Load ‘1’ H Load ‘0’ HIGH voltage level HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition LOW voltage level LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; ...

Page 5

... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I supply current CC ΔI additional supply current CC C input capacitance I = −40 °C to +125 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage ...

Page 7

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay see see pulse width CP HIGH or LOW; W see LOW; see recovery time MR; see rec set-up time D to CP; see 74LVC1G175 Product data sheet Single D-type flip-flop with reset ...

Page 8

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t hold time D to CP; see maximum CP; see max frequency power dissipation capacitance [1] Typical values are measured the same as t and PLH PHL [ used to determine the dynamic power dissipation (P PD × ...

Page 9

... NXP Semiconductors 12. Waveforms D input CP input Q output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical output voltage drops that occur with the output load Fig 7. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the set-up, the CP to ...

Page 10

... NXP Semiconductors Table 9. Measurement points Supply voltage 1. 2.7 V 2 3 5.5 V Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. ...

Page 11

... NXP Semiconductors 13. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.8 0.20 0.10 OUTLINE VERSION IEC SOT363 Fig 10. Package outline SOT363 (SC-88) 74LVC1G175 Product data sheet Single D-type flip-flop with reset; positive-edge trigger ...

Page 12

... NXP Semiconductors Plastic surface-mounted package (TSOP6); 6 leads y 6 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) UNIT 0.1 1.1 0.40 0.26 mm 0.013 0.9 0.25 0.10 OUTLINE VERSION IEC SOT457 Fig 11. Package outline SOT457 (SC-74) 74LVC1G175 Product data sheet Single D-type flip-flop with reset; positive-edge trigger ...

Page 13

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 14

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 13 ...

Page 15

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 16

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 17

... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74LVC1G175 v.4 20101004 • Modifications: Added type number 74LVC1G175GN (SOT1115/XSON6 package). • ...

Page 18

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 19

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC1G175 Product data sheet Single D-type flip-flop with reset ...

Page 20

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Package outline ...

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