74LVT574DB,112 NXP Semiconductors, 74LVT574DB,112 Datasheet - Page 3

• Manufacturer Part Number: 74LVT574DB,112
• Description: IC OCTAL D TRANSP F-F 20SSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr
• Type: D-Type Busr

Specifications of 74LVT574DB,112

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 150MHz
• Delay Time - Propagation: 3.6ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Logic Family: LVT
• Technology: BiCMOS
• Number Of Bits: 8
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Non-Inverting
• Operating Supply Voltage (typ): 3.3V
• Package Type: SSOP
• Propagation Delay Time: 6.6ns
• Low Level Output Current: 64mA
• High Level Output Current: -32mA
• Frequency (max): 150MHz
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LVT574DB; 74LVT574DB; 935170730112

NXP Semiconductors
5. Pinning information
Table 2.
74LVT_LVTH574_4
Product data sheet
Symbol
OE
D0 to D7
GND
CP
Q0 to Q7
V
Fig 4.
CC
Pin configuration for SO20, and (T)SSOP20
Pin description
GND
OE
D0
D1
D2
D3
D4
D5
D6
D7
5.1 Pinning
5.2 Pin description
10
1
2
3
4
5
6
7
8
9
74LVTH574
74LVT574
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
001aae758
20
19
18
17
16
15
14
13
12
11
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
CC
Rev. 04 — 11 September 2008
Fig 5.
(1) The die substrate is attached to this pad using
Description
output enable input (active LOW)
data input
ground (0 V)
clock pulse input (active rising edge)
data output
supply voltage
74LVT574; 74LVTH574
conductive die attach material. It can not be used as a
supply pin or input
Pin configuration for DHVQFN20
index area
terminal 1
D0
D1
D2
D3
D4
D5
D6
D7
3.3 V octal D-type flip-flop; 3-state
Transparent top view
2
3
4
5
6
7
8
9
74LVTH574
74LVT574
GND
(1)
19
18
17
16
15
14
13
12
001aah711
© NXP B.V. 2008. All rights reserved.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
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