74ABT273ADB,112 NXP Semiconductors, 74ABT273ADB,112 Datasheet - Page 2
![IC OCTAL D-TYPE F-F 20SSOP](/photos/6/52/65221/20-ssop_sot339-1_sml.jpg)
74ABT273ADB,112
Manufacturer Part Number
74ABT273ADB,112
Description
IC OCTAL D-TYPE F-F 20SSOP
Manufacturer
NXP Semiconductors
Series
74ABTr
Type
D-Type Busr
Datasheet
1.74ABT273AD118.pdf
(12 pages)
Specifications of 74ABT273ADB,112
Function
Master Reset
Output Type
Non-Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
350MHz
Delay Time - Propagation
3ns
Trigger Type
Positive Edge
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74ABT273ADB
74ABT273ADB
935185620112
74ABT273ADB
935185620112
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
20-Pin Plastic DIP
20-Pin plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
1995 Sep 06
Eight edge-triggered D-type flip-flops
Buffered common clock
Buffered asynchronous Master Reset
Power-up reset
See 74ABT377 for clock enable version
See 74ABT373 for transparent latch version
See 74ABT374 for 3-State version
ESD protection exceeds 2000 V per Mil Std 833 Method 3015 and
200 V per machine model.
Octal D-type flip-flop
SYMBOL
I
t
t
C
CCH
PLH
PHL
IN
PACKAGES
GND
Propagation delay
CP to Qn
Input capacitance
Total supply current
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
10
1
2
3
4
5
6
7
8
9
PARAMETER
TEMPERATURE RANGE
20
19
18
17
16
15
14
13
12
11
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
V
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
CC
C
V
Outputs High; V
SA00052
I
L
= 0V or V
= 50pF; V
OUTSIDE NORTH AMERICA
2
CC
T
CC
amb
74ABT273A PW
74ABT273A DB
CC
DESCRIPTION
The 74ABT273A has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered Clock (CP)
and Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
All outputs will be forced Low independent of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where the true output only is required and the CP and
MR are common elements.
PIN DESCRIPTION
= 5V
74ABT273A N
74ABT273A D
CONDITIONS
3, 4, 7, 8, 13,
2, 5, 6, 9, 12,
= 25 C; GND = 0V
=5.5V
NUMBER
14, 17, 18
15, 16, 19
PIN
10
20
11
1
SYMBOL
D0 - D7
Q0 - Q7
GND
V
MR
CP
CC
NORTH AMERICA
7ABT273APW DH
74ABT273A DB
74ABT273A N
74ABT273A D
Clock pulse input (active rising edge)
Data inputs
Data outputs
Master Reset input (active-Low)
Ground (0V)
Positive supply voltage
NAME AND FUNCTION
TYPICAL
150
3.0
3.4
3.5
74ABT273A
Product specification
DWG NUMBER
853-1774 15704
SOT146-1
SOT163-1
SOT339-1
SOT360-1
UNIT
pF
ns
A