74LVC377PW,112 NXP Semiconductors, 74LVC377PW,112 Datasheet

IC OCT D FF POS-EDG TRIG 20TSSOP

74LVC377PW,112

Manufacturer Part Number
74LVC377PW,112
Description
IC OCT D FF POS-EDG TRIG 20TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Type
D-Type Busr
Datasheet
1.74LVC377PW118.pdf (16 pages)

Specifications of 74LVC377PW,112

Function
Standard
Output Type
Non-Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
150MHz
Delay Time - Propagation
1.5ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC377PW
74LVC377PW
935210680112
1. General description
2. Features
3. Quick reference data
The 74LVC377 is a low-voltage, Si-gate CMOS device superior to most advanced CMOS
compatible TTL families.
The 74LVC377 has eight edge-triggered D-type flip-flops with individual inputs (D) and
outputs (Q). A common clock input (CP) loads all flip-flops simultaneously when data
enable input (E) is LOW. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the
flip-flop. Input E must be stable only one set-up time prior to the LOW-to-HIGH transition
for predictable operation.
Table 1:
GND = 0 V; T
Symbol Parameter
t
t
C
f
PHL
PLH
max
I
74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 05 — 21 February 2005
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50
Complies with JEDEC standard:
ESD protection:
Specified from 40 C to +85 C and from 40 C to +125 C
,
JESD8-B/JESD36 (2.7 V to 3.6 V)
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
propagation delay CP to
Qn
input capacitance
maximum clock
frequency
Quick reference data
amb
= 25 C.
transmission lines at 125 C
Conditions
V
R
V
CC
CC
L
= 500
= 3.3 V; C
= 3.3 V
L
= 50 pF;
Product data sheet
Min
-
-
-
Typ
4.6
5.0
330
Max
-
-
-
Unit
ns
pF
MHz

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74LVC377PW,112 Summary of contents

Page 1

Octal D-type flip-flop with data enable; positive-edge trigger Rev. 05 — 21 February 2005 1. General description The 74LVC377 is a low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. The 74LVC377 has eight edge-triggered D-type ...

Page 2

Philips Semiconductors Table 1: GND = Symbol Parameter used to determine the dynamic power dissipation ( input frequency in MHz output frequency ...

Page 3

Philips Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration SO20 and (T)SSOP20 6.2 Pin description Table 3: Symbol GND ...

Page 4

Philips Semiconductors 7. Functional description 7.1 Function table Table 4: Operating mode Load 1 Load 0 Hold Do nothing [ HIGH voltage level HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L ...

Page 5

Philips Semiconductors 9. Recommended operating conditions Table 6: Symbol Parameter amb 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground ...

Page 6

Philips Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current LI I quiescent supply current CC ...

Page 7

Philips Semiconductors Table 8: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t hold time maximum clock frequency max t ...

Page 8

Philips Semiconductors Table 8: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t hold time maximum clock frequency max t ...

Page 9

Philips Semiconductors 12. Waveforms Fig 4. Propagation delay clock (CP) to output (Qn), pulse width clock (CP) and maximum Fig 5. Data set-up and hold times of data input (Dn) and enable input (E) and pulse width Table 9: Supply ...

Page 10

Philips Semiconductors Fig 6. Load circuitry for switching times Table 10: Supply voltage V CC 1.2 V 2 3.6 V [1] The circuit performs better when R 9397 750 14589 Product data sheet Octal D-type flip-flop ...

Page 11

Philips Semiconductors 13. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 12

Philips Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1.80 mm ...

Page 13

Philips Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

Page 14

Philips Semiconductors 14. Revision history Table 11: Revision history Document ID Release date 74LVC377_5 20050221 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • Table ...

Page 15

Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

Page 16

Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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